What are the multiple drivers in this code?

Question

Code:

module controller_module(st_rst, clk, mem_rst,dis_rst, pe_rst, two_rst, three_rst, count, state ,two_end, s_end_1, s_end_2 , s_end_3, s_end_4, s3_end_22, s3_end_21, s3_end_12 ,s3_end_11, en_dis, 
 input_11, input_12, input_13, input_14,
 input_21, input_22, input_23, input_24,
 input_31, input_32, input_33, input_34,
 input_41, input_42, input_43, input_44,
 filter_11, filter_12, filter_13 ,
 filter_21, filter_22, filter_23 , 
 filter_31, filter_32, filter_33);
 input clk, st_rst;
 output two_end;
 output wire mem_rst, pe_rst, two_rst, three_rst, dis_rst;
 reg pe_rst, two_rst, three_rst, mem_rst, dis_rst;
 
 output s_end_1, s_end_2, s_end_3, s_end_4;
 output s3_end_22, s3_end_21, s3_end_12, s3_end_11;
 output en_dis;
 output [7:0] input_11, input_12, input_13, input_14,
 input_21, input_22, input_23, input_24,
 input_31, input_32, input_33, input_34,
 input_41, input_42, input_43, input_44,
 filter_11, filter_12, filter_13 ,
 filter_21, filter_22, filter_23 , 
 filter_31, filter_32, filter_33;
 
 
 reg two_end;
 reg s_end_1;
 reg s_end_2;
 reg s_end_3 ;
 reg s_end_4 ;
 reg s3_end_22 ;
 reg s3_end_21 ;
 reg s3_end_12 ;
 reg s3_end_11;
 reg [7:0] input_11, input_12, input_13, input_14,
 input_21, input_22, input_23, input_24,
 input_31, input_32, input_33, input_34,
 input_41, input_42, input_43, input_44,
 filter_11, filter_12, filter_13 ,
 filter_21, filter_22, filter_23 , 
 filter_31, filter_32, filter_33;
 
 reg en_dis;
 output[2:0] state;
 reg [2:0] state; 
 output [5:0] count; 
 reg [5: 0] count;
 
 reg [2:0] next_state; 
 
 //counter
 always @ (posedge clk )
 
 begin
 if(st_rst == 1'b1) 
 count <= 0; **//here**
 else
 count <= count + 1;
 end
 //state change
 always @ (posedge clk)
 begin
 if(st_rst == 1'b1)
 state <= 3'b101;
 else
 state <= next_state;
 end
 //mode change
 always @ (state, count)
 begin
 case(state) 
 3'b101://reset & initialize
 begin
 mem_rst =1'b1;
 dis_rst =1'b1; 
 pe_rst = 1'b1;
 three_rst = 1'b1;
 two_rst = 1'b1; 
 next_state = 0;
 two_end = 1'b0;
 s_end_1 = 1'b0;
 s_end_2= 1'b0;
 s_end_3 = 1'b0;
 s_end_4 = 1'b0;
 
 s3_end_22 = 1'b0;
 s3_end_21 = 1'b0;
 s3_end_12 = 1'b0;
 s3_end_11 = 1'b0;
 en_dis = 1'b0;
 input_11=1; 
 input_12=2; 
 input_13=3; 
 input_14=4;
 input_21=5; 
 input_22=6; 
 input_23=7; 
 input_24=8;
 input_31=9; 
 input_32=10; 
 input_33=11; 
 input_34=12;
 input_41=13; 
 input_42=14; 
 input_43=15; 
 input_44=16;
 filter_11=1; 
 filter_12=2; 
 filter_13=3;
 filter_21=4; 
 filter_22=5; 
 filter_23=6; 
 filter_31=7; 
 filter_32=8; 
 filter_33=9;
 
 
 end
 
 3'b000://start when st_rst changes to 0
 begin
 mem_rst = 1'b0; 
 dis_rst = 1'b0; 
 pe_rst = 1'b0;
 three_rst = 1'b0;
 two_rst = 1'b0; 
 count = 0; ***//here***
 next_state = 1;
 
 end
 3'b001://pe mode
 begin
 if(count == 6'd10)
 begin
 pe_rst = 1'b1;
 end
 
 else if(count == 6'd11)
 begin
 pe_rst = 1'b0;
 s_end_1 = 1'b1; 
 end
 
 else if(count == 6'd20)
 begin
 pe_rst = 1'b1;
 end
 
 else if(count == 6'd21)
 begin
 pe_rst = 1'b0;
 s_end_2 = 1'b1;
 end
 
 else if(count == 6'd30)
 begin
 pe_rst = 1'b1;
 end
 
 else if(count == 6'd31)
 begin
 pe_rst = 1'b0;
 s_end_3 = 1'b1;
 end
 
 else if(count == 6'd41)
 begin
 pe_rst = 1'b1;
 s_end_4 = 1'b1;
 next_state = 2;
 count = 0;
 end
 end
 3'b010://3by3 mode
 begin
 if(count == 9)
 begin
 s3_end_22 = 1'b1;
 end
 else if(count == 10)
 begin
 s3_end_21 = 1'b1;
 end
 else if(count == 13)
 begin
 s3_end_12 = 1'b1;
 end
 else if(count == 14)
 begin
 s3_end_11 = 1'b1;
 end 
 else if(count == 16)
 begin
 next_state = 3;
 count = 0;
 end
 end
 
 3'b011://2by2 mode
 begin
 if(count == 16)
 two_end = 1'b1; 
 else if(count == 18) 
 begin
 next_state = 4;
 count = 0;
 end 
 end
 
 
 3'b100://display mode
 begin
 en_dis = 1'b1; 
 next_state = 4;
 count = 0;
 
 end
 
 
 endcase
 end

Error:

[DRC MDRV-1] Multiple Driver Nets: Net cont/Q[0] has multiple drivers: cont/count_reg[0]__0/Q, and cont/count_reg[0]/Q.(5 more like this)

Why does the variable "count" have the multiple driver net? I checked the netlist, and under count which locates the //counter line, and //starts when st_rst changes to 0 occurred the problem.

Answer 1

You make assignments to count from 2 different always blocks. You must only make assignments to a signal from one always block, otherwise you have contention ("multiple drivers").

The sequential always block looks fine: @ (posedge clk )

You should remove the assignments to count from the combinational always block: always @ (state, count)

If you need to set count to 0 under other conditions, you could add them to the sequential block.