Connected to Multiple Drivers Problem Verilog

Question

After I synthesize it, the error occured like this:

Multi-source in Unit <BCDcountmod> on signal <BCD0<3>>; this signal is connected to multiple drivers.>

Any solution? (Here's below my code)

module BCDcountmod(
 input Clock, Clear, up, down,
 output [3:0] BCD1_1, BCD0_0 );
reg [3:0] BCD1, BCD0;
//reg [3:0] BCD1_1, BCD0_0;
always @(posedge Clock) begin
 if (Clear) begin
 BCD1 <= 0;
 BCD0 <= 0;
 end
end
 always @(posedge up) begin
 if (BCD0 == 4'b1001) begin
 BCD0 <= 0;
 if (BCD1 == 4'b1001)
 BCD1 <= 0;
 else
 BCD1 <= BCD1 + 1;
 end
 else
 BCD0 <= BCD0 + 1;
 end
always @(posedge down) begin
 if (BCD0 == 4'b0000) begin
 BCD0 <= 4'b1001;
 if (BCD1 == 4'b1001)
 BCD1 <= 4'b1001;
 else
 BCD1 <= BCD1 - 1;
 end
 else
 BCD0 <= BCD0 - 1;
 end
 assign BCD1_1 = BCD1;
 assign BCD0_0 = BCD0;
endmodule

Answer 1

Here, the signal BCD0 is being assigned values under 3 separate 'always' processes. Hence the synthesis is returning multiple driver error. Try moving all assignments of BCD0 signal under a single 'always' process. That will solve the issue. You could use different conditions under the same always block itself to define the behaviour of the signal.

The BCD counter which you are trying to implement is sensitive to clock edges, clear, up as well as down signals. So the process should be sensitive to clock edges and all other signals can be sensed w.r.t clock edges. One way of rewriting the code is like:

always @(posedge Clock) begin 
 if (Clear) begin 
 BCD1 <= 0; 
 BCD0 <= 0; 
 else if (up == 1) begin 
 if (BCD0 == 4'b1001) begin 
 BCD0 <= 0; 
 if (BCD1 == 4'b1001) 
 BCD1 <= 0; 
 else 
 BCD1 <= BCD1 + 1; 
 end 
 else 
 BCD0 <= BCD0 + 1; 
 end 
 else if (down == 1) begin 
 if (BCD0 == 4'b0000) begin 
 BCD0 <= 4'b1001; 
 if (BCD1 == 4'b1001) 
 BCD1 <= 4'b1001; 
 else 
 BCD1 <= BCD1 - 1; 
 end 
 else 
 BCD0 <= BCD0 - 1; 
 end 
 end 
end 

Here, all sensitivity conditions of both BCD0 and BCD1 signal are captured under a single 'always' block which will synthesize it properly.

• user2020598: could you please elabore it? it's not easy for me to separate it that easy. not only BCD0 is being multi-source but BCD1 either.
• Avin: Ok. i will edit my comment above
• Avin: @user2020598 Please have a look at the above answer and tell me if it helps.
• Avin: @user2020598 Were you able to get the code synthesized?