What does ' #period ' mean in Verilog code?

Question

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What does #period indicate or mean in Verilog in general terms? I have posted the image just as an example.

• Mitu Raj: Timing control which is not synthesisable.

Answer 1

# is a timing control that can be used to add a delay in the simulator.

In your example, the duration of the delay is specified by timescale * period.

period has no special meaning. It's simply a localparam that holds the constant expression 20:

• localparam period = 20;

According to the comment, the timescale has a unit of 1ns.

The timescale configuration should look something like this:

• `timescale 1ns/1ps

Therefore the expression after #period; is delayed by 1ns * 20 = 20ns.

Answer 2

#period can have different meanings depending on the context where it is used.

In the example provided, it is a delay event control placed in front of an empty procedural statement. That means it suspends the currently executing process for 20 time units until proceeding to the statement that follows it.

#period can also be used

• as a gate delay: not #period (out,int);
• continuous assignment delay: assign #period A = B + C;
• as a parameter value override in a module instance:

mymod #period mm(...);
...
module mymod #(P=0)(...);
endmodule