when do we use disable statement in verilog? is it possible to disable a block outside that block?

Question

I want to disable a block by using an if condition outside that block. I am getting error:

UNEXPECTED DISABLE EXPECTING ASSERT

Answer 1

Short answer: don't, especially if you want synthesisable Verilog.

Long answer: 'disable' is for tasks and named blocks, not modules. It has slightly suprising semantics: see http://verilog.renerta.com/source/vrg00012.htm ; somewhat similar to 'break'. It's not very idiomatic verilog.

If you're trying to build a normal computational logic block that has an enable signal, wrap all your logic in if (enabled) begin ... end.

• twinkle: i tried giving that am getting an error GENERATE IF STATEMENT SHOULD BE A CONSTANT EXPRESSION. Actually my aim is to instantiate a module 54 times or 24 times depending on wether the a signal d=0 or 1.But am not able to do this using if else condition
• pjc50: Modules are always instantiated. Think real hardware: transistors don't go away when you're not using them. You have to instantiate the module but just leave it to do nothing if you don't need it. If your 0 or 1 is actually a constant you could make it a parameter. (It would help if you posted the verilog..)
• twinkle: i understand that the modules will be present in hardware even if i give if else condition.But there will be wastage of power if the module works when its output is not required rite?
• pjc50: Yes; although your synthesis tools may turn an enable into some clock gating to save power. If it's a very large block you can power gate it. Are you targeting ASIC or FPGA?
• pre_randomize: Anything is possible, but what you are trying to do does not make sense for idiomatic verilog.

Answer 2

A common use for disable in your verilog testbench might be:

fork : wait_or_timeout
 begin : timeout
 #10_000; //#10ms
 $display("Timeout");
 $finish();
 disable wait_for_signal;
 end
 begin :wait_for_signal
 @(posedge SIGNAL);
 disable timeout;
 end
join

Here we start 2 parallel processes, the simulator will not execute any further code until both complete. Using disable, the first to complete disables the other.

For improved modularity and code reuse Generate Statements can be used. These are compile time constants though, they do not disable or powerdown hardware, they make hardware exist or not exist based on constant configuration options before running your sim or synthesis.

For power saving techniques, the use of enables in your flip-flops with auto-clock gating options for synthesis can result in good power savings.

always @(posedge clk or negedge reset_n) begin
 if (~reset_n) begin
 //reset
 end
 else if (enabled) begin
 //<= nextvalue;
 end
 // no final else, if not enabled hold value
 // this allows clk to be stopped
end