Verilog - use a clock signal as a value in its own procedural block

Question

I tried synthesizing the following code and was surprised to see that it doesn't work (at least with Vivado 2017.2).

module top(
 input wire clk,
 output reg dout
);
 always @(posedge clk) begin
 dout <= clk;
 end
endmodule

It complains with the error: use of clock signal in expression not supported.

Why is this? Shouldn't the value of clk be guaranteed to be 1 in its own posedge procedural block? Or, is this a race condition because skew could lead to the clock arriving before the data input?

Edit On second thought this isn’t all that surprising since this is very likely to violate the register’s setup timing requirement.

• DKNguyen: If it's always 1 then why don't you just set it to 1? Or is this just an experiment? Clock signals do have their own dedicated clock routing network. It just be that the route network doesn't branch off to go to the flip-flop inputs. I don't know that for a fact though.
• MattHusz: This is just a minimal example. I use it in a different context where it simplifies the logic slightly. The difference is minor, but I was more just curious.

Answer 1

Xilinx recommends in their coding guidelines that clock signal should not have combinational logic on their path. Whenever you write an expression with clock, you are generating a combinational logic with clock as one of the inputs.

Clocks have dedicated global routing in FPGA, which synthesiser may not be able to utilise if you bring combinational logic on their path.