Verilog generate block error

Question

I have a CORDIC module that I want to instantiate/generate 8 times, basically, I need 8 blocks of CORDIC. So, I have wrote the following statement block, but I get an error:

Error: Syntax error near cordic.

What am I doing wrong?

genvar k;
 generate
 for (k = 0; k < 8; k = k + 1)
 begin
 always @(posedge fpga_clk)
 begin
 cordic CDC(fpga_clk, rst, phase_word[k], sin_out[k], cos_out[k]);
 end
 end
 endgenerate

Answer 1

You cannot, and there is no need to put the cordic module instantiations inside an always block.

genvar k;
for (k = 0; k < 8; k = k + 1)
 begin : block
 cordic CDC(fpga_clk, rst, phase_word[k], sin_out[k], cos_out[k]);
 end

This create instances block[0].CDC through block[7].CDC of the cordic module. We assume that module already has always processes inside it, and they get instanced 8 times as well.

• eldenlord9394: Thanks. I understood that there is no need of always block or clock edges to make copies of a module. @dave_59