Use Xilinx Primitive elements in Verilog inside ISE

Question

I generated Verilog Post-Route simulation model of my original Verilog module, using Xilinx ISE.
It will generate a Verilog module using LUT and fpga level primitives such as IBUF,X_LUT4, ...

When trying to compile this code directly and synthesis it inside ISE itself, it cannot find Xilinx primtivies and assert compilation error such as ERROR:HDLCompilers:87 - "test.v" line 26 Could not find module/primitive 'X_OPAD'.

I want to know how can I include related modules/libraries inside ISE verilog code to avoid compilation errors.
Part of code is brought below:

module tripler (
 TRIPLED_OUTPUT, INPUT_SIGNAL
);
 output TRIPLED_OUTPUT;
 input INPUT_SIGNAL;
 wire INPUT_SIGNAL_IBUF_23;
 wire GATE3_OUT_0;
 wire GATE1_OUT_0;
 wire GATE2_OUT_0;
 wire GATE4_OUT_0;
 wire GATE5_OUT_0;
 wire GATE6_OUT_0;
 wire \TRIPLED_OUTPUT/O ;
 wire \INPUT_SIGNAL/INBUF ;
 wire GATE3_OUT;
 wire GATE1_OUT;
 wire GATE2_OUT;
 wire GATE4_OUT;
 wire GATE5_OUT;
 wire GATE6_OUT;
 wire TRIPLE_OUT;
 wire VCC;
 X_OPAD #(
 .LOC ( "PAD1" ))
 \TRIPLED_OUTPUT/PAD (
 .PAD(TRIPLED_OUTPUT)
 );
 X_OBUF #(
 .LOC ( "PAD1" ))
 TRIPLED_OUTPUT_OBUF (
 .I(\TRIPLED_OUTPUT/O ),
 .O(TRIPLED_OUTPUT)
 );
 X_IPAD #(
 .LOC ( "PAD2" ))
 \INPUT_SIGNAL/PAD (
 .PAD(INPUT_SIGNAL)
 );
 INPUT_SIGNAL_IBUF (
 .I(INPUT_SIGNAL),
 .O(\INPUT_SIGNAL/INBUF )
 );
 X_BUF #(
 .LOC ( "PAD2" ))
 \INPUT_SIGNAL/IFF/IMUX (
 .I(\INPUT_SIGNAL/INBUF ),
 .O(INPUT_SIGNAL_IBUF_23)
 );
 X_BUF #(
 .LOC ( "SLICE_X0Y13" ))
 \GATE3_OUT/XUSED (
 .I(GATE3_OUT),
 .O(GATE3_OUT_0)
 );
 X_BUF #(
 .LOC ( "SLICE_X0Y13" ))
 \GATE3_OUT/YUSED (
 .I(GATE1_OUT),
 .O(GATE1_OUT_0)
 );

• mng: Why are you trying to synthesize a simulation model? X_ modules are from the Xilinx simulation library, they are not device primitives.
• Nicholas Clark: What are you trying to accomplish by using X_ macros directly? Are you looking to do something that can't be done with the 'normal' primitive set (IBUF/OBUF/etc) ?

Answer 1

Primitives with prefix "X_" don't look like normal primitives.

I tried once to hide pins from top-level. So I instantiated IPAD and OPAD primitives in VHDL by hand.

Results:

• Synthesis XST -> complained about black-boxes
• Translate -> complained about black-boxes
• Map -> was very happy
• P&R -> run as normal
• BitGen -> run as normal
• test on FPGA -> all as expected

Xilinx has several primitive libraries:

• UNISIM
• UNIMACRO
• UNIPRIM
• ...

I don't know if there is also a documentation for XST/iSim, but I found this for Synth/xSim (Vivado): Vivado Design Suite User Guide - Logic Simulation (UG900). Have a look at pages 14 ff. It lists all libraries and when they are bound in simulation (post synth. / post impl.)

• VSB: I did include SIMPRIM modules (modules to simulate post place & route delays) to my design which include those X_BUF and ... modules. However Xilinx is now compalining about missing item which is glbl module. I added it as well but it seems that ISE ignore it. glbl module is a module which is intended to drive reset pins of all elements inside FPGA. However I don't know what is missing. Currently I added Name glbl module to my code however here is Xilinx compiler complaint: 'glbl.GTS' could not be resolved !
• Paebbels: There is a -insert_glbl switch in the Simulation Process Properties. Parameter description: Automatically Insert glbl Module in the Netlist - I never change such things, maybe it helps.