how to do a shift/add multiplier in verilog?

Question

I tried this

module sum(X,Y,Q);
 input [31:0] X,Y;
 output [31:0] Q;
 assign Q=X+Y; 
endmodule
module register(loadD, clk, rst, Q);
 input [31:0] loadD;
 input clk, rst;
 output reg [31:0] Q;
 always@(posedge clk, posedge rst) begin
 if(rst) begin
 Q<=0;
 end
 else if(clk) begin
 Q<=loadD;
 end
 else begin
 Q<=Q<<1;
 end 
 end
endmodule
module multiplier(A,B,andS,regS,clk,rst);
 input [31:0] A,B;
 input clk,rst;
 output [31:0] andS, regS;
 sum BL1(A,B,andS);
 register BL2(andS,clk,rst,regS);
 assign A=regS&{32{B[0]}};
endmodule

But don't work

• The Photon: What situation do you expect to lead to the shift operation happening in the register module? Re-read your code and see if it will do what you expect.
• Oldfart: Feels like homework to me. Do you know the shift, add, multiply algorithm? Because what is here is a far from what you need.
• Alan S: hm, I'll try fix the code. The simulation is not what I expect.. the code is just doing a sum.

Answer 1

If there is a

posedge clk

in the sensitivity list of an always block, the condition

if(clk)

will be always true. And

else begin
 Q<=Q<<1;
end

will never be deployed.

Answer 2

The logic in your register module seems incorrect. The sensitivity list you use requires a rising edge on either clk or rst, so one or both of these will be high when the module is activated. Now look at your if...else if...else logic and think about how you want that to work.

Answer 3

As pointed out by Elliot, The problem appears in the lines

if(rst) begin
 Q<=0;
end
else if(clk) begin
 Q<=loadD;
end
else begin
 Q<=Q<<1;
end 

If you are detecting both the clock and reset in the sensitivity list, then why you want to check again for a clock? Read a similar answer here: Clock usage in the always block and in the event