Multi-bit tri state buffer in verilog not working

Question

I'm trying to write a tri-state buffer that buffers more than one bit, this is what I currently use:

assign _memIn[7:0] = (_memRW == 0) ? memOut[7:0] : 1'bzzzzzzzz;

But it doesn't work. It is supposed to assign memOut, which is a [7:0] register to _memIn which is a [7:0] wire connected to inout, when _memRW is 0 (which it is always supposed to be, I checked using the logic viewer thing). But it only partially works. Whenever memOut is either 0 or 1, everything works fine, but if I set it to 2, _memIn becomes x.

I have absolutely no idea why, and am hoping someone can help.

I should note that I assign _memIn twice.

Above assign is in my testbed, and this assign is in my actual module:

assign _memIn[7:0] = (_memRW == 1) ? memOutC[7:0] : 1'bzzzzzzzz;

Don't know if that is the issue, if it is, how do I fix it?

The idea is that the second assign snippet is in my "CPU", so if _memRW is 0, it means read from memory, if it's one, do nothing.

Then in my testbed, I "emulate" a RAM chip by checking if _memRW is 0, if it is, then assign a register containing the correct mem value to _memIn. If it's 1, write to memory.

Answer 1

I strongly suggest you try 8'bzzzzzzzz; as you vector is 8 bits wide, not 1 bit.

• Tim: Thanks! That works. I didn't even know the first digit was the amount of bits. I probably should update that in my entire code.