System Verilog Mux Implementation using tri-state buffers

Question

I found a verilog implementation of a mux using tri-state buffers in the document UMD Lab Tutorial on Verilog (I'm not a student, graduated 2 years ago :))

module mux(input wire [7:0] in0,
 input wire [7:0] in1,
 input wire [7:0] in2,
 input wire [7:0] in3,
 input wire [1:0] sel,
 output reg [7:0] out)
assign out = (sel == 2'b00) ? in0 : 8'bZ ,
 out = (sel == 2'b01) ? in1 : 8'bZ ,
 out = (sel == 2'b10) ? in2 : 8'bZ ,
 out = (sel == 2'b11) ? in3 : 8'bZ ;
endmodule

When I tried this with SystemVerilog, I got the multiple driver error.

Can someone show me alternate code? I know using case statement will simplify things. I'm just wondering if its possible with tri-state and if we can physically implement mux with tri-state buffers on an Fpga platform.

• Elliot Alderson: Does this answer your question? SystemVerilog Mux design with "always_comb and tri state variables"
• Mitu Raj: you probably used output out, which means output var logic out, which doesn't support multiple drivers. What you need is output wire logic out or simply output wire.
• nebuchadnezzar_II: @ElliotAlderson, I asked the previous question as well. Now I'm clear.

Answer 1

You can fix the compiler error by changing output reg to output wire. See this post explaining why multiple drivers are not allowed to the same variable.

But FPGAs typically do not support tri-state drivers within the device. You can certainly do this on a bus between FPGA devices.

• nebuchadnezzar_II: It works now thanks!! I was also seeing if fpgas use tri-state buffers, found that these units are mostly used at output bidirectional pins and buses. I guess I was intending to use this kind of implementation when I encounter designing bus logic.