Clock usage in the always block and in the event

Question

In general, if we are working on a sequential circuit, say a Flip Flop (e.g. D Flip Flop) The code we write for the always block part is:

 always @(posedge clk or posedge reset)
 begin
 if (reset) begin
 // Asynchronous reset when reset goes high
 q <= 1'b0;
 end else begin
 // Assign D to Q on positive clock edge
 q <= d;
 end
 end

I am confused on the point - Why the line if(clk) is not used/written/introduced before q <= d in our always block. Motivation: Posedge transition corresponds to transition from:

• 0 to 1
• x to 1
• z to 1
• 0 to x
• 0 to z

So, why in most of the sequential codes, we don't confirm that the positive edge of the clock has appeared after the edge transition from low to high. I've searched the forum for this topic but can't find a specific answer on this. I am a newbie and will appreciate your guidance.

Answer 1

You have a valid point. If we were being very careful we would want to know if the clock or reset was actually in the X state, and we would probably set Q to X if that was the case.

So why don't we do those checks? The clock and reset are signals that we design very carefully to ensure that they are solid digital signals, with fast transitions from 0 to 1. So, it is often safe to assume that they are never X for a significant length of time.

If you do want to be a careful designer, it is usually better to check for unknown values of clock and reset at their point of origin rather than everywhere they are used. Adding assertions for these signals in just one part of the design allows the simulations to be much for efficient than adding complex if/then/else checks in millions of flip flops.

Answer 2

It's implied that if the block triggered, and reset is not high, that clock rising edge must have triggered the always block (because the always block triggered either because posedge reset or posedge clk). Basically if reset is high, you want to behave like a reset no matter what in the always block, otherwise you want to behave like a flip flop.

• Animesh Srivastava: I appreciate your answer, please can you guide me why does one not confirm whether my clock has made a transition from low to high and has achieved a positive level value? Since we need both a transition from low (0) to high (1) and not to any intermediate state.
• vicatcu: You are free to, but it's redundant in the code you provided. If reset is not HIGH in the always block CLK must be high. Otherwise the always block wouldn't have executed. Also, think about how this is actually used in real life. At startup, yo assert Reset for some period of time (long enough for it to propagate and initialize everything), at which point CLK is definitely running. Indeterminate state of CLK is not a realistic possibility.
• toolic: 0 to x on clk is a posedge where clk=x, not clk=1.
• The Photon: @toolic, that might be useful (or a problem) in a testbench. But in a physical circuit there isn't any X state. (The X state means the simulator can't predict which level the signal has. It doesn't model metastable or invalid logic states)