I write this module to arithmetic shift to left and right in verilog

Question

this is my code:

module zero(out,A,B);
 output signed[5:0] out;
 input signed[5:0] A,B;
 assign out = A[5:0]<<<2 + B[5:0]>>>1;
endmodule

but the output is always zero.

is there anything wrong?

(I don't want to use @always)

• jsotola: is this a school assignment?
• The Photon: Can you share your testbench?
• Elliot Alderson: How do you know that the output is always zero?
• mohamadreza: I am new to hardware description languages and because of this i can't handle this @jsotola
• Elliot Alderson: Please answer the three questions that were asked in the first three comments to your question. Even if you are new to HDL you should be able to answer these questions.

Answer 1

From our discussion in comments, it seems the problem is operator precedence. According to this, + has higher precedence than <<<, so your expression will calculate (A <<< (2 + B)) >>> 1 rather than what you might expect.

This can be solved by adding parentheses to ensure the expected order of operations.