wrong operation result in shift right arithmetic in verilog

Question

If I simply write following code:

module TOP;
wire [31:0] a = 32'b11111111_11111111_11000000_00000000;
wire [31:0] b = 32'b00000000_00000000_00010000_00011111;
wire [4:0] shamt;
assign shamt = b[4:0];
wire signed [31:0] signed_a;
assign signed_a = a;
wire [31:0] output;
assign output = signed_a >>> b;

This gives a correct result which is 11111111_11111111_11111111_11111111

However, if I use code that uses module, it always generates wrong result:

module TOP;
reg [31:0] a = 32'b11111111_11111111_11000000_00000000;
reg [31:0] b = 32'b00000000_00000000_00010000_00011111;
wire [31:0] out;
ALU alu(
 .A(a),
 .B(b),
 .C(out)
);
initial
begin
 #10 $display("out: %b\n", out);
 #10 $display("outout: %b\n", alu.outout);
 #10 $display("C: %b\n", alu.C);
end
endmodule
module ALU (
 input [31:0] A,
 input [31:0] B,
 output [31:0] C
);
wire signed [31:0] outout;
wire [31:0] signed_a;
assign signed_a = A;
wire [4:0] shamt;
assign shamt = B[4:0];
assign outout = signed_a >>> shamt;
assign C = outout;
endmodule

In above code, all result from $display shows wrong value which is

00000000_00000000_00000000_00000001.

Why it doesn't generate correct value like first code?

Answer 1

You need to define signed_a as signed in the ALU module:

wire [31:0] signed_a;

should be

wire signed [31:0] signed_a;

Answer 2

Your problem is down to simple typos.

In your second code you have places where you use singed_a, and others where you use signed_a. If you check the warnings from your compiler it will actually tell you this.

Basically your code ignores the input A because you are assigning it to a non-existent variable.

Secondly, your second code uses a bit shift (>>), not an arithmetic shift (>>>) so will not perform sign extension (see below).

---

(削除) The result your second module calculates is exactly the correct result for the hardware you have described. (削除ここまで)

>> is the bit shift operator, which performs zero filling. It doesn't matter whether the number is signed or unsigned, it will shift in zeros to the MSBs.

The >>> operator on the other hand is an arithmetic shift. This will perform sign extension, shifting in the MSB of the original number into the MSBs.

• sungjun cho: Sorry, I made a mistake. It was >>> not >>. Even though I use >>> in the second code, it doesn't show correct result.