Verilog: Shift Register with feedback loop

Question

I am trying to simulate a 3 stage shift register with feedback loop using D-flipflop and XOR gate.

main.v:

module main(
d0,d1,d2,
 clk ,
 reset ,
 q0,q1,q2);
input clk,reset;
inout d0,d1,d2,q0,q1,q2;
dff df1(.d(d0),.clk(clk),.reset(reset),.q(q0));
dff df2(.d(q0),.clk(clk),.reset(reset),.q(q1));
dff df3(.d(q1),.clk(clk),.reset(reset),.q(q2));
xor1 exor1(.a(q1), .b(q2), .c(d0));
endmodule

dff.v:

module dff(
d,
 clk,
 reset,
 q);
input d,clk,reset;
output q;
reg q;
always @ ( posedge clk)
 if (~reset) begin
 q <= d;
 end else begin
 q <= 1'b0;
 end
endmodule

main_tb.v:

module main_tb;
reg clk,reset;
 //reg d0,d1,d2,q0,q1,q2;
 wire d0,d1,d2,q0,q1,q2;
 initial
 begin
 clk = 0;
 reset = 1;
 #15
 reset = 0;
 end
always begin
 #5 clk = !clk;
 end
 main U0(
 .d0(d0),
 .d1(d1),
 .d2(d2),
 .clk(clk),
 .reset(reset),
 .q0(q0),
 .q1(q1),
 .q2(q2)
 );

endmodule

Now ISim doesnt simulate this code. Where am i going wrong?

EDIT: edited the testbench code. ISim is stuck at 0ps.enter image description here

• Tom Carpenter: Just for reference, the standard format for registers with synchronous reset is: always @ ( posedge clk) if (reset) begin q <= 1'b0; end else begin q <= d; end. Synthesis tools are better at recognising logic when you stick to the standard patterns.
• Dave Tweed: @TomCarpenter: It doesn't matter. To a synthesis tool, your version and the OP's version are exactly equivalent.

Answer 1

You have a reset signal in your code, but you never actually assert it.

Without that, the simulator cannot put the FFs into a known state, so they just show "unknown" forever.

Assigning values to your q wires in the testbench is useless — that just conflicts with the values that the dffs are trying to produce.

• Rohith Reddy: So all the values get initialized in ISim, but the 'Run' button is greyed out
• Rohith Reddy: Hey @Dave Tweed, Any idea on how to 'Run' it.
• Tony Stewart EE since 1975: In any LFSR if you reset to 0's then feedback must be inverted to D, otherwise it is stuck and that it wont work. If inverted feedback then all 1's is illegal for initial condition, with an odd number of XOR's

Answer 2

Your clock generator should be

 always @ // remove the (*)
 #5 clk = !clk;

Also, you probably want to use a procedural force statement and then release the intermediate q signals.

• Rohith Reddy: Where should I add force statement? In main.v or in main_tb.v?
• dave_59: In main_tb. You want to force the q0-1 for at least one clock cycle to get the shift register into a known state, then release them
• Rohith Reddy: initial begin clk = 0; reset = 0; force U0.d0 = 1'b0; force U0.q0 = 1'b0; force U0.q1 = 1'b1; force U0.d1 = 1'b0; force U0.d2 = 1'b0; #5 release U0.d0; release U0.q0; release U0.q1; release U0.d1; release U0.d2; end
• Tom Carpenter: Shouldn't need to force any signals, just assert the reset signal for a clock cycle or more.
• dave_59: I guess it depends on how you want to test the LFSR.