chip-design

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JackonYang / paper-reading

Star 251

比做算法的懂工程落地,比做工程的懂算法模型。

arxiv computer-architecture tvm mlir chip-design llm

Updated May 26, 2025
Jupyter Notebook

librelane / librelane

Star 139

ASIC implementation flow infrastructure

asic eda digital-design electronic-design-automation asic-design openlane chip-design librelane

Updated Oct 17, 2025
Python

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

asic rtl verilog finite-state-machine uart alu hdl verilog-hdl open-source-hardware serial-communication rtl-design digital-designs 8bit-cpu chip-design tinytapeout control-logic prototype-core embedded-core minimal-cpu-core

Updated Oct 9, 2025
SystemVerilog

patrickschulz / openPCells

Star 58

Parametric layout generator for digital, analog and mixed-signal integrated circuits

lua analog cadence integrated-circuits pcells parametric-cells chip-design layout-automation

Updated Oct 16, 2025
C

mabrains / sky130_klayout_pdk

Sponsor

Star 31

Skywater 130nm Klayout Device Generators PDK

custom-layout pdk pcells skywaters analog-layout chip-design

Updated Jul 12, 2024
Python

ttihp-verilog-template

TinyTapeout / ttihp-verilog-template

Star 21

Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects

verilog vlsi chip-design tinytapeout

Updated Apr 16, 2025
Verilog

arhamhashmi01 / rv32i-pipeline-processor

Star 20

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

vhdl verilog microprocessor vivado hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator rv32im asic-design chip-design 5-stage-pipelined-processor rv32i-processor

Updated Feb 19, 2025
Verilog

ojasvi-shah / Advanced-Physical-Design-Using-OpenLANE--Ojasvi-Shah

Star 15

Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah

virtualbox riscv vlsi openlane chip-design

Updated Oct 19, 2024

popovych-labs / open-npu

Star 15

Open NPU is an open-source project dedicated to creating a flexible, extensible, and high-performance neural processing unit (NPU) architecture. Open NPU aims to democratize access to cutting-edge neural processing technology for machine learning and AI applications.

asic ml high-performance-computing npu chip-design

Updated Jun 20, 2024

flaport / condalayout

Star 11

Conda + KLayout

design electronics layout conda eda chip klayout photonics epda chip-design

Updated Aug 21, 2022
Dockerfile

marcelwa / ls4ai

Star 10

Hack4Her: Logic Synthesis for AI

machine-learning ai fpga logic-synthesis chip-design

Updated Jun 13, 2025
Jupyter Notebook

XS-MLVP / xcomm

Star 8

xspcomm encapsulates the DPI-based digital circuit and provides various high-level language operation interfaces.

verification multilanguage chip-design

Updated Aug 14, 2025
C++

Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

Star 7

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

verification matrix-multiplication verilog systemverilog questasim logic-design sva systolic-arrays amba-apb functional-coverage chip-design

Updated Jun 26, 2024
Verilog

OJB-Quantum / Generative-Layout-Notebooks

Star 7

GDSII/OASIS layouts, including fractals, generated in working Google Colab notebooks. Layout previews are plotted as 2D graphics before exporting.

open-source automation google layout quantum gds metamaterials fractals lithography oasis microfabrication generative-design gdsii nanofabrication metamaterial-design colab-notebook quantum-hardware chip-design chip-design-automation gdstk

Updated Oct 16, 2025
Jupyter Notebook

gh0stintheshe11 / Static-Logic-PRSG-chip

Sponsor

Star 3

Carleton University / ELEC4609 Integrated Circuit Design and Fabrication / Project: Static Logic PRSG (Pseudo Random Sequence Generator) chip design, fabrication and testing.

chip-design pseudo-random-sequence-generator chip-fabrication chip-testing

Updated Aug 6, 2024

electricalgorithm / introduction-to-VHDL-projects

Sponsor

Star 1

VHDL Projects that I've created during the course Programmable Logic Devices in West Pomeranian University of Technology in Szczecin.

mux comparator seven-segment traffic-light-controller chip-design digtial-design adder-circuit line-buffer ring-counter four-digit-seven-segment-driver

Updated May 30, 2022
VHDL

DolbyUUU / Awesome-Surveys-of-LLM4EDA

Star 1

A curated list of surveys, reviews, and awesome lists on the application of Large Language Models (LLMs) and AI for Electronic Design Automation (EDA) and chip design.

eda electronic-design-automation chip-design llm ai4eda llm4eda domain-specific-llms

Updated Sep 7, 2025

zukhri2106 / 8-Bit-computer-CPU-Design

Star 0

A 8-bit computer CPU is designed using Logic Circuit software. Logic Circuit is educational software for designing and simulating digital logic circuits.

chip-design