A framework for formally verifying distributed systems implementations in Coq
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Jan 27, 2026 - Rocq Prover
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Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity to trace failures to root cause.
mcp static-analysis waveform eda rtl verilog systemverilog uvm vcd verdi fsdb hardware-verification root-cause-analysis llm-tools rtl-verification chip-verification model-context-protocol mcp-server pyslang simulation-debugging
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Sep 8, 2026 - Python
An implementation of a simple asynchronous message-passing lock server, verified in Coq using the Verdi framework
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Oct 23, 2017 - Coq
Created a RISC-V Pipelined processor in SystemVerilog with features like Caches, Prefetching, History Table. Skills employed: SystemVerilog, Verdi, Logic Design, Computer Architecture
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Jul 2, 2023 - HTML
Verdi framework runtime library
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Dec 16, 2022 - OCaml
UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol
c fpga i2c verilog spi vivado systemverilog uvm verdi microblaze axi hardware-description-language basys3-fpga synopsys-vcs
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Jul 24, 2025 - VHDL
A verified system transformer for serialization of Verdi systems using the Cheerios library.
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Aug 24, 2017 - Coq
Verdi-G Series control panel
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Jul 10, 2026 - Python
grep for waveforms — read signal values, clock frequency, and transitions from Synopsys FSDB, Cadence SST2, and open VCD dumps, straight from the shell. Deterministic output, runs locally, no viewer. CLI + MCP server + Claude Code skill.
cli mcp waveform eda verilog systemverilog gtkwave uvm vcd verdi ai-agents fsdb design-verification xcelium simvision sst2 llm rtl-simulation claude-code claude-code-skill
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Sep 8, 2026 - Python
Low-Power CGRA Design Methodology (WIP)
verilog vcs systemverilog synopsys hdl uvm hardware-acceleration parallel-processing low-power verdi cgra upf dvt uvm-verification uvm-testbench
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Apr 15, 2026 - SystemVerilog
32-bit RISC-V processor implementing out-of-order execution, register renaming, and precise retirement in SystemVerilog.
rtl systemverilog computer-architecture risc-v microarchitecture verdi rv32im synopsys-vcs synopsys-dc out-of-order-execution register-renaming
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Aug 13, 2026 - SystemVerilog
SPI/I2C Master-Slave RTL 설계 및 UVM 기반 검증 — Scoreboard PASS, Functional Coverage 100%, Logic Analyzer 실측 검증 포함
fpga i2c verification spi vcs systemverilog uvm verdi functional-coverage uvm-verification uvm-testbench
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Aug 11, 2026 - SystemVerilog
🛠️ Implement distributed consensus protocols for reliability and fault tolerance in systems, focusing on Paxos, Raft, and PBFT for performance analysis.
python java rocksdb distributed-systems consistency key-value async raft cryptocurrency tokio bft kvstore hunt paxos hacktoberfest raft-consensus-algorithm verdi kv-store brpc replicated-state-machine
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Sep 8, 2026 - C++
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