A dynamic verification library for Chisel.
testing coverage scala verification chisel constrained-random-verification functional-coverage bus-functional-model chisel-test timed-assertions
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Nov 9, 2024 - Scala
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functional-coverage
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Python packages providing a library for Verification Stimulus and Coverage
python coverage randomization constraints constrained-random cocotb verification-stimulus random-stimulus functional-coverage
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Feb 18, 2026 - Python
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
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Feb 16, 2026 - VHDL
Python API to Unified Coverage Interoperability Standard (UCIS) Data
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Feb 19, 2026 - Python
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
verification matrix-multiplication verilog systemverilog questasim logic-design sva systolic-arrays amba-apb functional-coverage chip-design
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Jun 26, 2024 - Verilog
UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.
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Feb 26, 2025 - Verilog
Configurable AXI4 Verification IP developed using UVM, featuring reusable master and slave agents, protocol checking, functional coverage, and scoreboard-based verification.
protocol randomization vip scoreboard systemverilog questasim uvm axi amba sva axi4 functional-coverage uvm-verification constrained-randomization asserti
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Feb 3, 2026 - SystemVerilog
Simple and Complete UVM TestBench For Verification Of S R Latch
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Jun 19, 2021 - SystemVerilog
RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.
python jenkins cpu processor verification dpi spike riscv isa vcs systemverilog uvm constrained-random sva rv32im questa functional-coverage
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Aug 20, 2025 - SystemVerilog
UVM-based verification of an AHB-to-APB bridge, validating protocol compliance, address decoding, data integrity, error handling, and corner cases using constrained-random testing and functional coverage.
randomization bridge verilog scoreboard systemverilog protocols uvm amba apb ahb functional-coverage constrainted-randomization
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Jul 12, 2025 - SystemVerilog
UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.
makefile verification vcs systemverilog fifo cdc uvm testbench sva metastability functional-coverage async-fifo questa-sim
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Aug 22, 2025 - SystemVerilog
UVM verification environment for an I2C controller (constrained-random + assertions + functional coverage) — Questa/ModelSim
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Jan 9, 2026 - VHDL
Complete UVM TestBench For Verification Of Ring (Onehot) Counter
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Jun 19, 2021 - SystemVerilog
Dual Port RAM - Verification in System Verilog and Functional Coverage
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Jul 27, 2025 - SystemVerilog
A robust SystemVerilog implementation of a configurable Data Aligner module, accompanied by a comprehensive UVM (Universal Verification Methodology) testbench.
systemverilog digital-logic-design universal-verification-methodology functional-coverage rtl-verification
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Jan 30, 2026 - SystemVerilog
RV32I RISC-V core written in SystemVerilog, with an emphasis on coverage-driven verification using constrained-random stimulus, SVA assertions, and functional coverage
cpu fpga verification assertions riscv rtl vivado systemverilog risc-v rv32i design-verification constrained-random-verification cpu-simulation functional-coverage systemverilog-assertions systemverilog-constraint
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Feb 20, 2026 - SystemVerilog
FIFO Verification Environment built with SystemVerilog, leveraging Object-Oriented Programming (OOP) for robust testbenches, including comprehensive Functional Coverage and SystemVerilog Assertions (SVA) for thorough design validation.
coverage verification assertions verilog fifo uvm testbench system-verilog object-oriented-programming digital-design hardware-verification functional-coverage
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Jun 26, 2025 - SystemVerilog
AHB to APB Bridge Design and UVM-based Verification as per AMBA specifications.
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Feb 20, 2026 - JavaScript
SystemVerilog testbench with assertions and coverage for verifying AXI4-Lite protocol compliance. Simulated using Vivado XSIM CLI with WSL2.
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Jun 25, 2025 - SystemVerilog
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