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@tmeissner
tmeissner
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Home-Office

T. Meissner tmeissner

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Home-Office
FPGA-Engineer doing design and verification using VHDL, SystemVerilog, SVA and PSL.

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@VHDL

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tmeissner /README.md

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  1. psl_with_ghdl psl_with_ghdl Public

    Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

    VHDL 66 7

  2. libvhdl libvhdl Public

    Library of reusable VHDL components

    VHDL 28 5

  3. formal_hw_verification formal_hw_verification Public

    Trying to verify Verilog/VHDL designs with formal methods and tools

    VHDL 43 7

  4. vhdl_verification vhdl_verification Public

    Examples and design pattern for VHDL verification

    VHDL 15 1

  5. cryptocores cryptocores Public

    cryptography ip-cores in vhdl / verilog

    VHDL 41 13

  6. ghdl/ghdl ghdl/ghdl Public

    VHDL 20089387 simulator

    VHDL 2.7k 403

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