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@SeanS4
SeanS4
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Sean Stimpfle SeanS4

πŸŽ“ Computer Engineering @ UIUC β€’ '27 πŸ’» SystemVerilog β€’ C/C++ β€’ Assembly πŸ“§ sstimpfle323@gmail.com

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SeanS4 /README.md

Featured Projects Seeking 2027 Hardware Roles


RISC-V Processor Physical Design πŸ“ŽοΈŽ ASIC / VLSI
Bit-sliced RISC-V datapath built with custom standard cells, alongside automated place and route in Cadence Innovus.
Virtuoso Innovus Calibre DRC/LVS CMOS Tcl FreePDK45
Bluetooth-Controlled FPGA Tetris πŸ“ŽοΈŽ FPGA / Embedded
FPGA Tetris with BRAM-backed board state and HDMI output; ESP32 microcontroller processes inputs via Bluetooth.
SystemVerilog Vivado ESP32 C++ BRAM Timing Closure XDC

Unix-Like Operating System πŸ“ŽοΈŽ Systems Software
RISC-V OS with user processes, Sv39 virtual memory, system calls, preemptive scheduling, device drivers, and a filesystem.
C Device Drivers Assembly GDB UART VirtIO Trap Handling
Out-of-Order Processor πŸ“ŽοΈŽ RTL / Microarchitecture
Synthesizable RV32IM core with register renaming, dynamic scheduling, an LSQ/ROB, and precise in-order retirement.
SystemVerilog Synopsys VCS/DC Verdi SpyGlass Lint L1 Cache

Pinned Loading

  1. riscv-asic-physical-design riscv-asic-physical-design Public

    32-bit RISC-V ASIC physical design featuring a custom standard cell library, bit-sliced datapath routed in Cadence Virtuoso, and automated Cadence Innovus implementation.

    Tcl

  2. bluetooth-fpga-tetris bluetooth-fpga-tetris Public

    FPGA Tetris implemented in SystemVerilog with HDMI output and Bluetooth controls through an ESP32-WROOM-32.

    SystemVerilog

  3. unix-like-operating-system unix-like-operating-system Public

    Unix-like RV64 operating system with Sv39 virtual memory, preemptive multitasking, system calls, KTFS storage, VirtIO drivers, and a user shell.

    C

  4. rv32im-out-of-order-processor rv32im-out-of-order-processor Public

    32-bit RISC-V processor implementing out-of-order execution, register renaming, and precise retirement in SystemVerilog.

    SystemVerilog

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