Questions tagged [intel-fpga]
A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).
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What’s the recommended workflow to implement an FSM in Verilog and generate waveforms in Intel Quartus? (Beginner question)
I’m a complete beginner in FPGA and HDL design, and I’m starting a small project to control a 4-floor elevator using a finite state machine (FSM). My ultimate goals are:
1. Derive the equivalent logic ...
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Ethernet GMII MAC to MAC Loopback
I am trying to connect two MACs in GMII mode - using a SoC to connect them, and routing GMII signals through the Fabric.
In the spec for the Intel MAC GMII IP, it assumes connection to PHY.
This IP ...
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How to open the precompiled Quartus Prime project
I have precompiled (with db and incremental_db folders, so it have sof/pof files) Quartus Prime (22.1std.1 Build 917 02/14/2023 SC Lite Edition) project and want to open "Technology Map Viewer (...
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SDRAM to OCM via DMA on the Agilex 5
I am in the process of learning about communication between SDRAM and OCM via DMA, using the Agilex-5.
The idea will be to write 0xdeafbeef to the SDRAM, then ...
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Quartus internal oscillator
I have managed to implement the internal oscillator in the CPLD MAX II: EPM240T100C5. From what I can see it can be set to either
I have used the wizard to generate the code for 5.56 MHz. The files ...
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Reaction on signal changing using always block in Verilog not work after FPGA programming
I want to do synthesizable always block, that would execute code by d1 signal changing (posedge and ...
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Can I combine AS and JTAG headers for CycloneIV?
I'm using a CycloneIV E, and would like to have both JTAG and AS flash programming options available.
Do I need two headers, like Figure 8-28 suggests, or can these be combined, as the pins used for ...
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FPGA Reset Circuit after Download
What would be the easiest way to create a reset signal after new configuration has been downloaded to an FPGA?
I've always done a reset manually via a switch .. but there has to be a better way - ...
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FPGA Cyclone V GX Fails at Low Temperatures (-40C)
I am using an Altera Cyclone V FPGA (5CGXFC7D6F27I7N) on a custom carrier board to convert DisplayPort video (input) to BT.656 video data (output). The output video data is then sent to an encoder, ...
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How would a 4-bit full-adder be implemented in a Cyclone V FPGA?
I have this diagram from my class of how 3 6-input LUTs are used to create a Full 4-bit adder. It's not particularly clear, but each 6-input LUT has 2 outputs (so I suppose they're really operating as ...
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I2C Timeout Error on DE2-115 Board with ADS1115
I am working on a school project to build a 'weather station' out of a DE2-115 FPGA board and after covering almost everything, the project will not work with I2C.
I am using a NIOS-II to run the I2C ...
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Cyclone 10lp FPGA not configuring through Flash chip (EPCQ64A ), but configures ok through JTAG (.sof)
We have developed a cyclone 10 Lp FPGA (10cl016Y) board, the Schematic is shown below
The FPGA chip configures good through JTAG using .sof file, but if the Flash chip is programmed using .jic file, ...
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Decrease system clock frequency in Quartus II?
How to decrease system clock frequency in Quartus II from standard 50 MHz to 2 Hz (two clock fronts per second)?
I find out it easier using constraints editing way, namely, SDC (Synopsys Design ...
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Found illegal assignment group name conflicts with top-level node name
How to fix the follow errors was appeared after pin assingment (in Pin Planner window) and project compilation:
"Error: Found illegal assignment group name "key" -- conflicts with top-...
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2DFF synchronizer output was determined to be a clock by timing analyzer
I'm the newbie in FPGA.
I want to design a frequency counter, so the design will involved some CDC problem.
Therefore, I used FIFO (I use the Quartus FIFO IP) and 2DFF synchronizer in my design.
Below ...