What’s the recommended workflow to implement an FSM in Verilog and generate waveforms in Intel Quartus? (Beginner question)

Question

I’m a complete beginner in FPGA and HDL design, and I’m starting a small project to control a 4-floor elevator using a finite state machine (FSM). My ultimate goals are:

1. Derive the equivalent logic circuit.

2. Synthesize the design and produce timing/waveform outputs in Intel Quartus.

This is the State Diagram:

Elevator state diagram

Specific Questions:

What order should I follow?

Should I write the FSM directly in Verilog based on my state diagram or first derive the state‐bit and output‐logic equations by hand from the truth table, then translate those equations into Verilog?

I haven't made any progress on the project yet due to a lack of necessary information. I would appreciate any guidance or mentorship, as well as general advice or tips, to help me move forward with this and future endeavors.

Answer 1

Both are valid.

For learning purposes, it helps to do it by hand, because you are now transferring your theoretical knowledge into a program, and following the same structure is beneficial for understanding here, as you can recognize the patterns in the simulation more easily.

In real world applications, you would not even assign binary values to states or inputs, and instead let synthesis derive these for you, because the goal shifts from "easy to follow for you" to "easy to follow for whoever needs to read that code after you."

It also often turns out during synthesis that the most bit-compact representation of states and inputs is not the most resource-efficient final design.

So I'd go with "both" for a few exercises, then skip the manual steps once you feel confident. What @toolic said about testbenches is also important.

Answer 2

I recommend trying to implement the FSM directly in Verilog based on your state diagram. You should have 2 Verilog modules:

• 1 module for the design
• 1 module for the testbench which will have an instance of the design

It is very important to run a Verilog simulation of your code with enough input combinations to stimulate all FSM transitions.

There are plenty of FSM Verilog code examples on this site, and elsewhere, that might help in getting you started.

Here is one example

Here is another example

Many of the examples use the EDA Playground site where you can run the example simulations. The site requires you to create a free account, but it is well worth it.