Stateful logic synchronization clock with memory read/writes

Question

I am working on a hobby project using Verilog and iCEstick evaluation board. I have a stateful logic (FSM) which needs to read and write to the on-chip block RAM. Now I am a little bit confused, it is not clear how to synchronize my FSM transitions and memory reads and writes. Lattice shows the following timing diagram in their Memory Usage Guide for iCE40 devices:

BRAM reading timing diagram for iCE40

On this diagram "external logic" sets the reading address on the falling edge of RCLK, while the memory captures the address for reading on the rising edge of the clock.

I am wondering if it is a good way to design access to memory in FPGA:

1. Have a shared clock, which clocks both FSM and memory (I think having the same clock domain is a great plus)
2. Do transitions between FSM states (which set READ/WRITE addresses, sets data to write and captures the data read from the BRAM) on the falling (negative) edge of the clock.
3. Assuming that all the timing restriction (setup and hold times) are honored, do memory access on the positive edge of the clock (I am targeting 50MHz clock in my design)

The alternative could be to only use positive edges for everything, but we need to set the address and data signal in advance and spend another tick of the clock keeping these signals stabilized. It seems to be slower (since in best case we only use every other clock tick for reading/writing), plus our FSM gets a little bit more complex, because we need extra FSM states for keeping memory inputs stabilized.

What are the best practices here? The first approach seems tempting, but are there any pitfalls?

Answer 1

No, there's no requirement that the address and control changes need to occur on the falling edge of the clock. You can in fact change the address on every clock edge and get valid data on every clock edge. You just need to make sure you understand the overall latency — which data relates to which address.

What the diagram is telling you is this: If your FSM puts out an address at rising edge N, the BRAM captures that address at rising edge N+1, and you can capture the corresponding data at rising edge N+2. Everything is fully pipelined; there are no wasted cycles.