FPGA Reset Circuit after Download

Question

What would be the easiest way to create a reset signal after new configuration has been downloaded to an FPGA?

I've always done a reset manually via a switch .. but there has to be a better way - perhaps there is a pin that informs that a download/soft reset has been performed that I could feed into an external timer? Or is there a way to do it from within Verilog maybe using an internal pin signal on the FPGA itself?

I'm using Cyclone IV FPGA.

Answer 1

You can generate a simple power on reset signal in the FPGA logic.

The Cyclone IV is capable of initialising a register on entry to user mode, so you can have a signal that is asserted high immediately after configuration completes.

Combined with an active clock to deassert the signal you can generate a simple reset signal in the FPGA

reg [3:0] resetGen;
initial begin
 resetGen <= 4'hF;
end
always @ (posedge clk) begin
 resetGen <= {resetGen[2:0], 1'b0};
end
wire reset;
assign reset = resetGen[3];

If you don't have an active clock available, the Cyclone IV includes an internal oscillator which can be used to provide a 40-80MHz clock signal (not very accurate but will do for this) which is used for configuration so is available immediately on entering user mode.

• SparkyNZ: I thought the "initial" keyword was only for testing rather than synthesis?
• SparkyNZ: Well - that certainly worked for me so I'll accept your answer as a solution.
• Tom Carpenter: @SparkyNZ initial used to set default values is synthesisble by many FPGA vendors tools. You can also alternatively do reg [3:0] resetGen = 4'hF;.

Answer 2

Read about the CONF_DONE pin in the FPGA datasheet. This pin outputs the state of the FPGA configuration and can be used as reset source.

• SparkyNZ: Thank you - that was what I was originally looking for but much to my surprise the "initial" keyword seemed to work as well.