Verilog Non-Blocking and IF statement mixed

Question

always @(posedge clk)
begin
 clk_counter <= clk_counter + 1;
 if(clk_counter == divider)
 clk_counter <= 0;
end

Will the clk_counter <= clk_counter + 1; and if statement be executed concurrently so the clk_counter evaulation at if statement will be the old one ?

Answer 1

The statements within a begin/end block execute sequentially. However, a nonblocking assignment statement evaluates the RHS as it executes and schedules an update to the LHS in a later event region.

If there are multiple updates scheduled to the same variable, last update wins. So this code executes effectively the same as

always @(posedge clk)
begin
 if(clk_counter == divider)
 clk_counter <= 0;
 else 
 clk_counter <= clk_counter + 1;
end

Answer 2

The if will be evaluated before any change is made to the clk_counter signal because the assignments are non-blocking.

The assignment of 0 to the clk_counter signal should take priority over the increment assignment because it happens afterwards.

Putting the increment into an else would have equivalent behaviour, whilst being clearer code.