Hardware implementation of Verilog Block & Non-blocking FSM

Question

I'm doing a FSM question from here: https://hdlbits.01xz.net/wiki/Fsm1s

enter image description here

I have implemented 2 different FSM using non-blocking and blocking for this question.

Non-blocking:

module fsm_nonblock(
 input wire i_clk,
 input wire i_rst,
 input wire i_enbl,
 output wire o_out
);
parameter STATE_B = 0;
parameter STATE_A = 1;
reg state;
assign o_out = (state == STATE_B)? 1:0;
always @ (posedge i_clk) begin
 if (i_rst)
 state <= STATE_B;
 else if (!i_enbl)
 case(state)
 STATE_B: state <= STATE_A;
 STATE_A: state <= STATE_B;
 endcase
endmodule

Blocking:

module fsm_block(
 input wire i_clk,
 input wire i_rst,
 input wire i_enbl,
 output reg o_out
);
parameter STATE_B = 0;
parameter STATE_A = 1;
reg present_state;
reg next_state;
always @(posedge i_clk)
 if (i_rst) begin
 present_state = STATE_B;
 next_state = STATE_B;
 o_out = 1;
 end
 else begin
 case(present_state)
 STATE_B:
 if (!i_enbl)
 next_state = STATE_A;
 STATE_A:
 if (!i_enbl)
 next_state = STATE_B;
 endcase
 present_state = next_state;
 case(present_state)
 STATE_B: o_out = 1;
 STATE_A: o_out = 0;
 endcase
 end
endmodule

My questions are:

1. Both FSMs produce the same output when the same inputs are given. From what I have understood, the hardware implementation of this Non-blocking FSM is: (I wonder this is correct?)

enter image description here

2. How is the hardware implementation of Blocking statement FSM? It would have 2 more registers? (additional register for next_state and output) How 2 registers (present_state & next_state) store the same data at the same clock? (If we look at the image below) Same as well for the output register, how it stores the output value in a register for another module to read it at the same posedge clk?

enter image description here

3. What are the pros & cons of using the blocking/non-blocking statements FSM?

4. If we do digital circuit design, which of the circuits (blocking & non-blocking) are preferred?

Answer 1

The first code example is how a state machine is customarily coded. It uses good coding practice regarding nonblocking assignments (<=) for the sequential logic (the flip flop). The top diagram which you label as "Non-blocking FSM" is a pretty good conceptual drawing of what the circuit would look like (maybe with enbl inverted).

However, the second coding example is not how a state machine is customarily coded. Looking at the HDLBits link you posted, I can understand why you coded it this way. But, I think that site is steering you wrong for this particular example. As I mentioned, nonblocking assignments should be used for sequential logic. Blocking assignments should only be used for combinational logic. Therefore, you should not use the second coding example.

There are many other questions on this topic, such as:

• How to interpret blocking vs non blocking assignments in Verilog?
• When to use blocking and non-blocking assignments

• Yee Yang Tan: Thank you very much! So, the compiler would generate the hardware which I have drawn for both Verilog code description? What about the "o_out"? If it is "reg o_out", how the hardware is represented?
• toolic: @YeeYangTan: You're welcome. I don't know how the 2nd code would compile (synthesize). Give it a try if you are really interested. reg does not always mean you infer a register (flip-flop) in synthesis.