In Verilog code, what happens when repeat statement exists inside always statement with posedge?

Question

For example,

always @(posedge clk)
begin
 repeat (20)
 @(posedge clk) ;
end

In this statement, when the clk is triggered at first time, repeat statement will be executed. However, if the clk is triggered next time, does it mean that there are two running repeat statements?

Answer 1

A 'posedge' (or other) condition only becomes effective (can be triggered again) if the events triggered by it have finished.

Thus the first posedge will start the repeat condition. After 20 "posedges" the one at the top can be triggered again.

---

A question popped up:
Yes, it is complete legal Verilog and can be used in test benches.

This is probably a more useful example:

always @(posedge signal)
begin 
 <do something>
 // ignore any posedges of signal for the next 20 clock cycles
 repeat (20)
 @(posedge clk);
end

• sungjun cho: Thks! But, I have one more. Let's assume that the always block is triggered by posedge clk as well as other signals, if always block is triggered by posedge clk, then even though other signals come in while it is executing, then always block is not triggered until repeat (20) is finished?
• Oldfart: All the conditions in the always @(...) section are ineffective until the code triggered by one or more of them it has finished.
• Tom Carpenter: @sungjuncho correct. For simulation constructs like this, everything in the always block executes sequentially. Until it reaches the end, it will never start again - even if that causes it to miss events.
• Itachi Uchiha: this is bit late but what if I have always@(*) repeat (5) #a = 5 ; b = 4; # a= 4 ; b = 5; and in Testbench a = 4 and b = 5 initially

Answer 2

Here is an example I just found from this Chinese Blog: Runoob verilog: loop

In the code provided, an 8-bit continuous loading circuit is implemented.

always @(posedge clk or negedge rstn) begin
 j = 0 ;
 if (!rstn) begin
 repeat (8) begin
 buffer[j] <= 'b0 ; //assign all 8 regs to 0, without delay
 j = j + 1 ;
 end
 end
 else if (enable) begin
 repeat (8) begin
 @(posedge clk) buffer[j] <= counter3 ; //assign @ nxt posedge clk
 j = j + 1 ;
 end
 end
end

In this example, with rstn set, buffer[j] <= counter3 is executed 8 times in 9 consecutive clk pos edges, and j loops from 0 to 8.

Based on the simulation, we find the top @(pose clk or negedge) would not be executed until its sub loop repeat(8) has finished.

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