Verilog port width larger than defined

Question

I simulated a design and viewed waveforms in Simvision, and an input port width is shown as in1[223:0]. But, it was declared as:

parameter BW = 13;
...
input [16*BW-1:0] in1;

I'm expecting it to be in1[207:0].

What are any reasons the port size would be changed by the simulator in Verilog?

Answer 1

A parameter value can be overridden when a module is instanced inside another module.

Since in1 is 224 bits wide, and since 224 = 16 * 14, the BW parameter is probably being overridden as 14 (BW = 14).

Refer to How to instantiate a module.