What is SystemVerilog equivalent for VHDL fixed_pkg and float_pkg?

Question

The VHDL fixed_pkg and float_pkg provide some very interesting functionality. The fixed_pkg is supported by some synthesis tools but the float_pkg is not supported at all. They basically provide a capability to declare a array of std_logic with positive and negative indices. This way one can create fixed point numbers and floating point numbers represented as array of std_logic.

I have not found anything like fixed_pkg and float_pkg for SystemVerilog so far. If something exists of this nature, where can I find it?

Answer 1

SystemVerilog does not really have the concept of baked-in libraries like VHDL has, neither does it support operator overloading and generic types which are used by the fixed_pkg package to implement fixed point types and math operations in VHDL with a 'native' feel / ergonomics.

There is however a synthesizable library (which I co-developed) that (ab)uses SV interfaces to implement a fixed point 'data type' that can be passed around modules. You don't get nice syntax like "c = a + b". Instead you instantiate interfaces which are your input/output fixed-point 'data types', and pass them to modules that perform addition/multiplication/resizing like this:

sfp #(1, 23) a(); // a = signed 1.23 (24 bits)
sfp #(8, 8) b(); // b = signed 8.8 (16 bits)
sfp #(5, 10) c(); // c = signed 5.11 (16 bits)
sfp_add my_adder (.in1(a), .in2(a), .out(a)); // Q1.23 + Q8.8 => Q9.23 => Q5.10

The example above adds a Q1.23 number a to a Q8.8 number b, internally shifting b to align the binary point, and then resizes the resulting Q9.23 number to a Q5.10 by truncating LSBs (flooring) and discarding (wrapping) or clipping MSBs.

See the README for more examples: (https://github.com/SkyworksSolutionsInc/fplib)

• quantum231: I am quite confused why SV does not have a built in data type for this. Or am I missing something?

Answer 2

I think you can seemlessly use real, shortreal for float values whereas int for fixed data type values to perform arithmetic operations on variables.

Below is the note from systemverilog-3.1a:

"The real and shortreal types are represented as described by IEEE 754-1985, an IEEE standard for floating point numbers (See [K1] in Annex K)"

As added in snip below, you can see sign, mantissa and exponent part structure. enter image description here

• user16145658: can anyone provide a good example of operator overloading in system verilog?, Does SystemVerilog support operator overloading? Never implemented and It's certainly not found in IEEE Std 1800-2017. Your quote from 7.17 Operator overloading represents illusory features.
• user16145658: SystemVerilog operator overloading (bind construct) #633
• quantum231: ok, I am very confused now, in VHDL we can bit vector with negative index representive fixed point numbers, I assume nothing like this can be done with SystemVerilog? Also, what is the proper way to convert between a vector of bits and float and vice versa? The typedef struct thing you presented is completely new information for me actually.
• Sourabh Tapas: @quantum231 bit vector is just concatenated bits. It depends on us what data type we define for it. For conversions "fx pt <->float pt" there are readily available IP cores by IntelFPGA/Xilinx. xilinx.com/support/documentation/ip_documentation/… intel.com/content/www/us/en/docs/programmable/683750/20-1/… IPs seamlessly supports fx <->float pt with option to manipulate bit vector width as per your need. i/p and o/p can be fixed or float anything.
• lyxicon: None of this is synthesizable which OP asked for.