Is there an analog of VHDL "wait-for-until" expression in the SystemVerilog Assertion?

Question

Suppose we have two signals: A and B. And we need to check that the rising edge of signal B is between 7.62ns and 7.77ns after the rising edge of signal A. In VHDL this can be done with two "wait-for-until" expressions.

1. Is it possible to write this with the SystemVerilog Assertion?
2. Is it possible to write this with the SystemVerilog Assertion without any additional clocks?

Answer 1

SystemVerilog does not have direct translation of the compound VHDL wait statements. The simple forms can be translated

• wait for delay → #delay
• wait on A → @A
• wait until expression → wait (expression)

If you needed to combine some of these forms together, they can be put into a fork/join_any block

VHDL:

wait until sig = 15 for 10 ns;

SV:

fork
 wait(sig == 15);
 #10ns;
join_any

SystemVerilog Assertions are not the best construct to catch timing errors, but they can be used

property p;
 realtime timestamp;
 @(posedge a) ('1, timestamp = $realtime) |=> 
 @(posedge b) $realtime - timestamp inside {[7.62ns:7.77ns]};
endproperty

• Arseniy: Am I right that the SV fork construction wait for the condition (sig==15) and THEN wait for 10ns and the VHDL wait-until-for construction wait 10ns waiting the condition (sig==15)?
• Ben Voigt: @Arseniy: That's what it would do without a fork.
• dave_59: fork/join_any block creates a process for each statement inside the block and waits for any one of the processes to complete before continuing after the block. In this case it is simply an OR of the conditions before continuing. Note that it does not terminate the remaining processes. There are other construct that can do that.