Using two different clocks in my assertion

Question

I am using SystemVerilog to write assertions in order to test the behavior of my design. In my design I have two clock : the usual CLK_int and another clock called I2C_IF_SCL_out. In the specification of my design:

SDA_Tick_shift= 01 for one CLK_int period, 10 CLK_int periods after falling edge of I2C_IF_SCL_out.

What I am asking is can I use two clocks in my clocking block @(posedge CLK_int) and @(I2C_IF_SCL_out)?

Answer 1

Assuming CLK_int has a much higher frequency than I2C_IF_SCL_out, what you probably want is

assert property (@posedge CLK_int $fell(I2C_IF_SCL_out) |-> ##10 SDA_Tick_shift==2'b01)

Otherwise, you would have to explain your requirements in much more detail.