Non overlapped implication(|=>) used in system verilog assertion

Question

I know that if I use

s1 |=> s2

the consequent sequence expression s2 will be evaluated on the next clock tick. However, if there is no clock(combinational circuit) how will the assertion be evaluated?Will the simulator wait for 1 time period and check s2 or is it something else?

Answer 1

There needs to be a clock declared somewhere. It can be declared in the sequence itself, the property calling the sequence, the assertion calling the property/sequence, or a default clocking block in the module/interface where the assertion/property/sequence resides.

You don't usually put assertions on conbinational logic. With RTL combinational logic you usually should not consider delay. Assertions are intended for flop to flop checking.

• dave_59: I wouldn't make that strong of a recommendation against using assertions in combinatorial logic. You might want to assert that a signal or set of signals maintain some legal set of values or relationships over all time without a clock (like one-hot). But you are correct to say that any assertion that has a cycle delay needs to have a defined clock.
• Greg: My recommendation to limit immediate assertions in RTL comb-blocks is base on: (1) they disappears in gate simulations and (2) may give false errors for zero-time glitches w/ noisy inputs and will degrades simulation performance with assertion coverage collection enabled. Usually, my one-hots go to a unique case statement; giving me a one-hot check that doesn't report zero-time glitches as errors, plus gives the intended full_case/parallel_case directive for synthesis. There is a place for assertions in comb-logic, my recommendation is to use them sparingly in RTL.
• dave_59: Not really logic assertions, but you might want to put un-clocked assertions on parameter values to make sure they are in an expected range.