How to get signal dependencies from RTL verilog?

Question

How can I find out if a signal B has any combinational dependency on a signal A without manually examining the verilog source code?

(Question edited to try and make the reason/background more clear)

In a complex design it can be easy to make mistakes and incorrectly get a dependency on a slow (but functionally correct) signal that is hard to notice or spot later. I'll try to draw a (highly simplified) example:

Preferred logic:
 ___________
A_FAST --->|--logic--|---> B_data
 | |
A_SLOW --->|--logic--|---> B_en
 ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈

Accidental logic:
 ___________
A_FAST --->| logic--|---> B_data
 | ^ |
A_SLOW --->|---/-----|---> B_en
 ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈

A_SLOW has accidentally sneaked into the logic and is not needed to determine B_data. However the timing for B_data becomes much slower than it has to be - it would be much better to use A_FAST. I would like to set up some check or assert to find unwanted combinational paths and so my question is:

Is there some easy way to find out if B_data has any dependency on a A_SLOW?

Perhaps get a list of all signal dependencies in the verilog rtl design? (Because that would be easy to scan through)

• Marcus Müller: the RTL is that dependency map...
• Oldfart: Sounds like an XY problem. The synthesis tools will remove any signals which do not contribute to a certain output. So you would be repeating work what is normally already done.
• Marcus Müller: If this is a real concern, you're probably not modularizing your system well enough, by the way.
• Oldfart: "and incorrectly get a dependency that is hard to notice or spot later." that is why you should test, test and test again your designs. As ASIC engineer I spend my time about:1% writing code, 95% testing and 4% general admin & coffee. It was not unusual for my testbench to be ten or more times bigger then the code
• Moberg: @Oldfart I want to find a slow dependency that does not cause any functional bug.

Answer 1

Static Formal tools are great at this. They have the ability to trace paths and validate assertions you make about them. There is a special segment of formal tools called connectivity checkers just for checking proper interconnect of the blocks that make up your SoC designs.

• Moberg: I have a hard time understanding if Questa connectivity check can do what I want. I updated my question so perhaps it's more clear now what I'm looking for. Also how could I use it or try it out? Do I have to pay for this tool?
• dave_59: If A_SLOW is truly not needed for the functionality of B, it should get optimized away. Why are you worried about it. Again, static timing tools can trace through paths after synthesis and tell you which ones will be a problem. I'm not aware of free tool that do this.
• Moberg: Sorry, I tried to clarify the question again (haha, will this ever end?). A_SLOW can be replaced with a faster signal (some part of it is needed so synthesis will not optimize it away). This time I was lucky that the path showed up in the timing report - but it could equally likely not have shown up and just made some other path slower due to time borrowing.

Answer 2

Look into Yosys, it might be possible to use for this.

Answer 3

If you have compiled your verilog with vcs, then u can run the simv executable with simv -ucli to get a cli to the simulation. In there you can for example do

> loads A -full

to get a list of all other signals that are driven by A. However it will only go 1 step, so if you want deeper dependency you'd have to iterate the command for each signal in the list.

See "Unified Command-Line Interface (UCLI)" in the VCS User Guide.