What is SystemVerilog way of writing the VHDL 'range attribute?

Question

In VHDL I can write this: slv_1(slv_2'range) so that I select slice of slv_1 that has same range as slv_2. In this example both slv_1 and slv_2 are actually std_logic_vectors.

I am writing SystemVerilog code. How is this done in SystemVerilog? I shall be grateful if you could guide me to the relevant LRM section.

logic [WORD0_TEXFORMAT_W-1:0] slv_1 = '0;
logic [$clog2(YUV_FORMATS_LIST_LENGTH)-1:0] slv_2 = '0;

I need to do slv_1[slv_2'range].

Answer 1

Refer to the $bits function in IEEE Std 1800-2023, section 20.6.2 Expression size system function.

module tb;
logic [31:0] slv = 'h1234_5678;
logic [ 7:0] yuv_slv = '0;
initial begin
 #1 $display("'h%x", slv[$bits(yuv_slv)-1:0]);
end
endmodule

Output:

'h78

Answer 2

Technically, the equivalent of VHDL slv_2'range is [$left(slv_2):$right(slv_2)]. See section 20.7 Array query functions in the IEEE 1800-2023 SystemVerilog LRM

But if you are just trying to make an assignment from a larger width to a smaller width, there is no need to do anything as Verilog will just implicitly truncate it:

slv_2 = slv_1;

You can also do an explicit truncate using a cast:

slv_2 = type(slv_2)'(slv_1);

• quantum231: What about slv_1[slv_2]?
• dave_59: @quantum231. What about it?. you need to be consistent. You description shows one set of names, but your code example shows another set of names.
• quantum231: you are right, I have made it consistent. Is slv_1[slv_2] legal SV or [$left(yuv_slv):$right(yuv_slv)]?
• quantum231: VHDL does not let larger to smaller, it is very specific about widths. SV allows different sizes and even different types to be assigned from one to another without throwing errors. Strange.
• dave_59: slv_1[slv_2] is not legal. I have updated my answer to match the identifiers in your question. To get stronger typing in SystemVerilog, see verificationacademy.com/topics/systemverilog/….