Creating entity/module containing IP from different vendors

Question

In FPGA design often we need to instantiate vendor specific IP. This could be simple things like Block RAM and DSP. It could be more complex things like FPU IP. The 3rd party IP is directly instantiated into the design where it is require to be used. This must be done when the infer from HDL does not work with the synthesis tool. Sometimes it might even be required to use specific VHDL attributes or something along those lines to give further instructions to the synthesis tool.

The problem comes where are creating a design that is supposed to be used across multiple vendors i.e be compiled in tools from Intel, Xilinx, Microsemi e.t.c. If we create a single design where we instantiate the modules from all the different vendors, it will not work with any tools since every tool will generate error about the 3rd party IP that it does not recognize. This happens even if use we VHDL generate statement that excludes all instances except one that is recognized by the current tool.

Now my question is, how do we create a module where some part that is intended for synthesis tool from another vendor, is ignored, and only the part relevant to the current tool is used. All synthesis tools might not support VHDL configuration. The method might actually differ between VHDL and SystemVerilog.

Answer 1

Honestly, this use case sounds complex enough that you will want to use a meta-build system that generates the project files depending on which toolchain you wish to use; and doing so, depending on the toolchain include the right files in the project.

Automating build configurations is a pretty common thing in software development, and thus, there's a few solutions for that. For example, Ettus' UHD FPGA code for the usrp3 class of devices uses Makefiles, which in turn call TCL scripts to set up vivado projects.

I hear good things about the award-winnning Edalize, which is an abstraction layer over different EDA tools, so that you only need to define your project once, and the toolchain-specific configuration differences.

• quantum231: The EDA tools used by hardware engineers are decades behind the software domain. So I guess the only way is to actually use scripting. I once met a person who told me that he created RTL file where some sections are commented out by a TCL or Python script just before compilation of the file to deal with this problem that I have described. I found that solution to be odd but it worked for him without too much trouble.
• Marcus Müller: @quantum231 exactly. And that's why projects like Edalize exist.
• gyuunyuu: There is also something called FuseSoC. I have not encountered anyone using these things so far.
• Marcus Müller: @gyuunyuu FuseSoC is a whole package manager for IP cores and SoC designs; it uses Edalize to define the build flows. Both are from the same main author.