Why does this file give me "syntax error: I give up." in verilog program?

Question

This is my original file saved as "example.v"

module example(a,b,y);
 input b,y;
 output a;
 assign a=b&y;
endmodule

This is my testbench file saved as "example_tb.v"

module testbench; 
 reg t_x, t_y; 
 wire t_z; 
 example DUT ( t_z, t_x, t_y ); 
 initial 
 begin 
 $dumpfile("example.vcd"); 
 $dumpvars(0, testbench);
 $monitor ($time, "t_x=%b, t_y=%b, t_z=%b",t_x, t_y, t_z); 
 #5 t_x = 1’b0; t_y= 1’b0; 
 #5 t_x = 1’b0; t_y= 1’b1; 
 #5 t_x = 1’b1; t_y= 1’b0;
 #5 t_x = 1’b1; t_y= 1’b1; 
 #5 $finish;
 end 
endmodule

Command I runned:

iverilog -o mysim example.v example_tb.v

Error reported:

example_tb.v:7: syntax error
I give up.

Answer 1

Your apostrophe chars are the problem

 $dumpfile("example.vcd");

should be

 $dumpfile("example.vcd");

And for all the literals, such as,

#5 t_x = 1’b0; t_y= 1’b0;

they should be

#5 t_x = 1'b0; t_y= 1'b0;

• Mitu Raj: Typical copy-paste bug!