Why does this file give syntax error in verilog?

Question

My original file has the following

module circuit_320a(A,B,C,D,N,F);
 output N,F;
 input A,B,C,D;
 wire w1,w2,w3,w4;
 and #(30) G1(w1,C,D);
 or #(30) G2(w2,w1,B);
 and #(30) G3(w3,w2,A);
 not #(30) G5(N,c);
 and #(30) G4(w4,B,N);
 or #(30)(F,w3,w4);
endmodule

and my testbench has these

`include "ask.v"
module t_circuit_320a_delay;
 wire N,F;
 reg A,B,C,D;
t_circuit_320a_delay M1 (A,B,C,D,N,F);
initial
 begin
 A=1'b0; B=1'b1; C=1'b0; D=1'b1;
 end
 initial #200 $finish;
 $dumpfile("ask.vcd"); 
 $dumpvars(0, ask_tb);
endmodule

When I try to compile I get syntax errors, why is that?

I have named the original file ask.v and the testbench ask_tb.v

Errors

• The Photon: Please share the complete error messages. It will make it much easier to find the problem.
• The Photon: One thing, you didn't name your last or gate like you did the other gates.
• user170589: @ThePhoton yes one moment please , see edits
• user170589: @ThePhoton Yes because it is the output of the schematic

Answer 1

You need to read the FAQ.

Specifically, the $ commands need to be in an initial block, to wit:

`include "ask.v"
module t_circuit_320a_delay;
 wire N,F;
 reg A,B,C,D;
 circuit_320a M1 (A,B,C,D,N,F);
 initial begin
 A=1'b0; B=1'b1; C=1'b0; D=1'b1;
 end
 initial #200 $finish;
 initial begin
 $dumpfile("ask.vcd");
 $dumpvars(0, t_circuit_320a_delay);
 end
endmodule

It will also help if you instantiate the correct module. t_circuit_320a_delay should be instatiating circuit_320a, not itself, and the $dumpvar call needs to refer to t_circuit_320a_delay, not the name of the file.

• user170589: I still get errors , please see the edit
• user170589: Neverimind I had a syntax error , wrote inital instead of initial