verilog modeling output x

Question

Lets consider the following code, I want to make the b x for #2 whenever a changes

module test();
reg [3:0] a;
initial 
begin
 $vcdpluson();
 a <=0;
 #5
 a <= 1;
 #5
 a <= 2;
 #1
 a <= 3;
 #4
 a <= 5;
end
reg [3:0] b;
always @(a)
begin
 b = 3'bx;
 b = #2 a;
end
endmodule

I am getting the following waveform from simulation

enter image description here

When a changes from 1->2 and 2->3, I expect the always block to get triggered(since the sensitivity list has only a). after #2 from 2->3 transition b should have become 3. But looks like after #1 b has become 3, it means the always @(a) loop didn't get triggered for the 2->3 transition of a. How to enable that ?

• Mitu Raj: You have to post complete waveform with signal names, not a part of it.

Answer 1

Your problem is you are using blocking assignments to write to b. That means your always @a procedure gets blocked for 2 time units before its able to see the next change on a.

By using a non-blocking assignment, the assignment gets queued, and the always procedure immediately goes back to the top waiting for the next change on a

always @(*)
begin
 b <= 3'bx;
 b <= #2 a;
end

• arun: even if you use non blocking statement it wont work
• Mitu Raj: What's the meaning of 'won't work'? , are the waveforms exactly the same? You haven't edited your question to include more details on waveforms after and before changes made to the code.@arun