Difference between always @ block and @ statement in Verilog

Question

I have not across the statement @(posedge clk) before. I would like to know how this statement is different from the always @(posedge clk) block which I am familiar with.

If I use a sensitivity list in a task for a Finite State Machine synthesis without always block; How is this different from a task with always block and sensitivity list?

As I understand both @ and always @ have the same functionality as both of them are always sensitive to the changes in the sensitivity list. Are there any differences with respect to simulation or synthesis?

Answer 1

The always @(posedge clk) statement is actually a combination of two statements:

The always procedural block:

always ... begin
 //Body of 'always' block
end

And a sensitivity list:

@(posedge clk) - At the positive edge of clk
@(signal or signal) - Any change in listed signals
@* - Any change to any signal used as an input to the block

When using Verilog for testbenches/simulation (this is not just SystemVerilog behaviour), you can use the always block on its own, for example

always begin
 #5 clk = !clk; //Create a clock of period 10 units
end

You can also use the sensitivity list on its own, in the form of a Procedural Timing Control:

initial begin
 @(posedge clk); //Wait for a pos-edge of the clock
 reset = 1; //Assert reset
 repeat(2) @(posedge clk); //Wait for two pos-edge of clock
 reset = 0; /Adeassert reset
end

Essentially this allows you to perform a sequence of test events based on say, a clock edge.

---

As far as I'm aware you can't use the procedural timing control for synthesis - instead a state machine or similar would be built within an edge sensitive always block.