Verilog code execution in gate level modeling

Question

The following is Verilog code an SR latch.

module SR_latch(Q, Qbar, Sbar, Rbar);
output Q, Qbar;
input Sbar, Rbar;
 
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
endmodule

I think that when an always block is used, it starts executing the code statements from top to bottom unless one is using nonblocking statements which execute in parallel. It's my understanding that an initial block which is used for testbenches always executes the code lines from top to bottom.

For the given code of SR latch, my question is that how the code lines get executed. They cannot start executing from top to bottom since the gate n1 needs Qbar as an input which comes from gate n2 which lies below n1.

• The Photon: Those are not "lines of code", they are a description of hardware.
• PG1995: I agree with you but still there would be a certain sequence in which they are executed when simulation is performed.

Answer 1

The initial and always constructs both instantiate procedural processes that execute concurrently; each construct creating an independent process. Within those constructs, there may be begin/end blocks where each statement within the block gets executed consecutively. Non-blocking assignments also execute consecutively within a begin/end block. It's just that the LHS does not get updated until a later region.

In gate-level modeling, each primitive you instantiate also creates a process that waits for an input to change, then schedules its output to update its value. In your example, something has to change the value of Sbar or Rbar to get the nand primitives scheduled to execute.

• PG1995: I'm sorry but I needed to clarify few related points. I thought it'd better to edit the question. I'd appreciate if you can help.