Questions tagged [computer-architecture]
Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.
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Why do DSP systems not use caches?
While studying for my Embedded System Design test I came across the following lines on the Wikipedia page on Harvard Architecture:
Digital signal processors (DSPs) generally execute small, highly ...
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Cascading 16‐to‐1 MUXes to build a 64‐to‐1 in Logisim: what to do with the 12 unused inputs and how to interpret the S[7:4]/S[5:4] notation?
I’m working in Logisim‐evolution 2.7.1 and I have to implement a 64‐to‐1 multiplexer using ONLY the built‐in 16‐to‐1 MUX components (I imposed this restriction).
The standard two‐level tree seems ...
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Why does the 2‐wire asynchronous handshake use this exact edge sequence?
1. Control Models
Master / Slave
The master controls the communication line (decides when to transmit or receive).
The slave transmits or receives under the master’s command.
Peer‐to‐Peer (symmetric)
...
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Deriving Master–Slave T Flip‐Flop state table
I’m trying to confirm the state‐transition table of a T flip‐flop
implemented with a master–slave pair of level‐sensitive D latches.
1 Ground‐truth table: positive‐edge‐triggered T FF
The 4 ×ばつ 4 ...
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Writes from PCIe device (Realtek ethernet NIC) to DRAM memory are not visible to core
Target: I am developing a baremetal driver for the Realtek Ethernet Controller (RTL8168g, MAC version 40) which is connected through PCIe to the SoC.
SOC Reference manual: https://developer.arm.com/...
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Implementation of Load Hazard in pipeline
Consider the following instruction sequence in a 5-stage pipeline with the stages: IF (Instruction Fetch), ID (Instruction Decode), EX (Execute), MEM (Memory Access), WB (Write Back)
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Confused about the usage of immediate encoding of branch instructions
I'm confused over the meaning of the immediate being stored as a multiple of 2 for branch instructions. So I'm working on a RISCV 32 bit project, I have a branch instruction that's supposed to jump 8 ...
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Loop unrolling when the number of Iterations is unknown
I've read that loop unrolling can improve CPU performance by reducing the overhead of loop control and enabling more instruction-level parallelism. When unrolling a loop, we perform multiple ...
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Why does my 4-bit ripple counter in Logisim always start at 1111, and how do I make it start at 0000?
I’m trying to build a 4-bit asynchronous (ripple) counter in Logisim Evolution 2.7.1 using four T–Flip-Flops, but I can’t get it to start counting from 0000. Instead, as soon as I click the clock the ...
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fully associative cache offset bit
I have a question regarding the offset bits in the cache example shown in the diagram.
From what I understand, we're using a 32-bit address, which is represented by 8 hexadecimal digits. The block ...
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How to build a proper Master-Slave T Flip-Flop using D Flip-Flops in Logisim?
I’m trying to correctly build a T Flip-Flop using a Master-Slave configuration in Logisim 2.7.1 win.
What I want:
I want to understand how to build a real T Flip-Flop using two D Flip-Flops connected ...
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Trouble implementing a T Flip-Flop (Master-Slave) in Logisim: output not toggling
I’m trying to design a T Flip-Flop using a Master-Slave configuration in Logisim 2.7.1 win.
I want to understand how to correctly build a T Flip-Flop using D Flip-Flops and an XOR gate.
What I’m doing:...
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Designing an Overlapping Mealy FSM to Detect the Pattern D–X–B–B
1. Problem Statement
Design a synchronous Mealy finite-state machine that scans a continuous stream of letters (A, B, C, D) encoded in two bits and asserts y=1 only ...
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What is the minimum electrical ICs you need to have to start the AM69 SoC from TI?
I cannot post on TI Design Forum because I don't have a TI-valid company email address.
I willl therefore ask the question here.
Introduction
TI offers a new type of SoC. It's called AM69. It's latest ...
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How to design a 32-Bit Floating point multiplier
My plan is to design a 32 bit floating point multiplier from scratch. I am still an undergrad with very beginner understanding in computer architecture, Verilog/VHDL and digital circuits/design.
Here'...