TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
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May 1, 2022 - C++
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cpu-simulator
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This is an HTML/Javascript CPU simulator and assembler for the CPU I designed. Originally, I created this CPU on paper many years ago for a homework assignment in college. More recently, I implemented my design in the Logisim logic simulator, and eventually it ran on an FPGA.
javascript html emulator simulator assembler assembly-language logisim cpu-simulator cpu-design computer-simulator logisim-cpu logisim-evolution
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Oct 1, 2023 - HTML
A small and simple 8-bit CPU built in Logisim. The project also includes an assembler and a manual for those who want to learn how a processor works.
cpu processor assembler logisim 8bit cpu-simulator 8-bit-cpu 8bit-cpu logisim-cpu logisim-evolution flip01
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May 12, 2025 - C++
The Mythical CPU Simulator for Real Students
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Dec 9, 2018 - Java
An educational resource that enables students to better visualize the execution of assembly code
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Oct 25, 2024 - Svelte
💡 WepSIM: Web Elemental Processor SIMulator 📱 💻 🖥️
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Oct 11, 2025 - HTML
A software simulator of how an OS might schedule processes
c-plus-plus templating process-scheduler object-oriented-programming process-scheduler-simulator cpu-simulator
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Nov 17, 2017 - C++
CPU Simulator written in Python
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Apr 8, 2020 - Python
Simulator for the MIC-1 CPU described in Andrew S. Tanenbaum’s textbook Structured Computer Organization
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Jun 21, 2022 - Java
RISC-V emulator/simulator in Python
python education processor-architecture cpu python3 riscv bare-metal risc-v baremetal cpu-simulator riscv32 riscv-linux riscv-simulator riscv-emulator rv32ima instruction-decoding risc-v-emulator risc-v-simulator system-emulation
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Aug 25, 2025 - Python
Simple Web-based 16-bit Microprocessor Assembler Simulator (8085 Working Progress)
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Apr 28, 2023 - JavaScript
Simulating the architecture of a computer in the terminal (Assembler + Simulator)
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May 11, 2020 - C++
Implementation of 8-Bit CPU based on Von-Neumann Architechture in HDL
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Nov 16, 2017 - Verilog
FISC V— built with Nothing but love❤️
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Jul 27, 2025
Assembler, ISA & everything else featuring the 16-Bit Minecraft Redstone CPU "Frostybte"
python minecraft cpu assembler redstone instruction-set-architecture cpu-simulator cpu-architecture minecraft-schematics
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Sep 23, 2025 - Python
Tera - A simulated ternary (base 3) CPU, assembly language, assembler and decompiler. Uses trytes made up of 9 trits rather than bytes of 8 bits.
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Sep 10, 2024 - C++
a goofy 8 bit cpu
cpu csharp assembly-language microcode instruction-set-architecture cpu-simulator custom-cpu logisim-computer logisim-evolution
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May 8, 2024 - C#
A GUI implementation of a CPU sim project originally developed by Wojciech S. Gac
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Jun 1, 2024 - Go
A translator to translate RV32I to REBEL-6. Includes custom assemblers to output RV32I (and hopefully soon REBEL-6) MRCS-readable object files, and assembly level simulators to simulate RV32I and REBEL-6 assembly code execution
riscv balanced-ternary ternary risc-v instruction-set-simulator rv32i cpu-simulator ternary-computer binary-to-ternary rebel-6 rv32i-to-rebel binary-to-ternary-translation instruction-set-translation c-to-ternary-pipeline ternary-computing
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Jun 16, 2025 - C++
A simple CPU simulator written in C & Python.
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Jun 9, 2025 - Python
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