The Synopsys ARC® VPX DSP IP family is optimized for the unique power, performance and area (PPA) requirements of embedded workloads such as IoT sensor fusion, radar and LiDAR processing, engine control, voice/speech recognition, natural language processing and other edge AI applications. The VPX processors are based on an enhanced ARCv2DSP instruction set and operate on 128-bit (VPX2, VPX2FS), 256-bit (VPX3, VPX3FS), 512-bit (VPX5, VPX5FS) and 1024-bit (VPX6, VPX6FS) vector words based on the same very long instruction word (VLIW)/single instruction-multiple data (SIMD) architecture.
The safety-enhanced ARC VPXxFS processor IP integrate hardware safety features including error correction code (ECC) protection for memories and interfaces, safety monitors and lockstep mechanisms that help designers achieve the most stringent levels of ISO 26262 functional safety compliance.
The VPX processors are supported by the Synopsys ARC MetaWare Development tools, including a vector length-agnostic software programming model specifically optimized for the VPX hardware architecture. The MetaWare compiler’s auto-vectorization feature transforms sequential code into vector operations for maximum throughput.
Scalable DSP processors for AI, IoT, automotive, and voice processing applications, featuring 128-bit, 256-bit, 512-bit, 1024-bit vector SIMD/VLIW, and floating point & math computation engines.
Scalable DSPs for safety-critical automotive applications. The processors feature a self-checking safety monitor, are ISO 26262 certified up to ASIL-D and ISO/SAE 21434 CyberSecurity compliant.
ARC processors are optimized to deliver the best PPA efficiency in the industry for embedded SoCs.
ARC processors are highly configurable, allowing designers to optimize the performance, power, and area of each processor instance on their SoC.
ARC Processors EXtension (APEX) technology enables users to customize their processor implementation.
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