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High-Performance, Mid-Range, and Ultra-Low Power RISC-V Processor IP

Synopsys ARC-V Processor IPTM is based on the open standard RISC-V instruction set architecture (ISA), extending the current ARC portfolio and giving customers access to the growing RISC-V ecosystem. Built on the success of multiple generations of ARC processor IP covering a broad range of processor implementations, including functional safety (FS) versions, the ARC-V portfolio delivers what you need to optimize and differentiate your SoC.

To accelerate software development, the ARC-V processors are supported by the trusted Synopsys MetaWare Development Toolkit. In addition, Synopsys’ extensive portfolio of EDA tools provide an out-of-the-box development and verification environment to help design and fully verify RISC-V-based SoCs.

Key Benefits

What's New

Article

Enhancing RISC-V Embedded Processor Performance through Advanced Instruction Fusion

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Article

How the RISC-V ISA Offers Greater Design Freedom and Flexibility

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Article

Enhancing RISC-V RVV with Custom DSP Instructions for Embedded Applications

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ARC-V Processor IP Families

RMX Series

32-bit embedded processors optimized for ultra-low power

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RHX Series

32-bit real-time processors with a high-speed, dual-issue 10-stage pipeline

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RPX Series

64-bit host processors with SMP Linux and L2 cache support

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Quotes from Synopsys ARC Customers and Partners

Resources

Connect with the Synopsys Processor IP Team

Connect with the Synopsys Processor IP Team

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