8-bit combinational ALU built from scratch with 3,488 CMOS transistors (KiCad + SPICE + Logisim + 1.24M tests
Design your own CPU, Operating system, and Compiler (Maintainer: Emin Ghuliev)
A RTL Synthesizer that can convert Verilog HDL into transistor-level netlist which can be simulated by Spice
🔥 This project performs a simulation of N and P-type MOSFET transistors. Next, the creation of logic gates is performed using the simulated transistors. Then, a Half-Adder mechanism is created with the logic gates, to later use it in a binary sum algorithm.
Project to build an 8-bit arithmetic logic unit (ALU) consisting only of transistors
This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert
NTUEE IC Design 23Fall HW2
SAT-related tools for digital circuit netlists described as granular transistors.
CMOS Standard Cell Library & 1-Bit Full Adder: A bottom-up digital design project using LTspice. Features transistor-level implementation of primitives (NAND/NOR/XOR) and hierarchical design of a 1-Bit Full Adder.
This project demonstrates the design and implementation of a Boolean expression using PMOS-only transistors in Microwind. It includes Boolean simplification, gate-level design, transistor-level schematic, stick diagram, Microwind layout, and simulation analysis with results and comparisons to CMOS
Transistor-level design and transient simulation of a 4-bit Ripple Carry Adder using CMOS logic in Cadence Virtuoso (90 nm GPDK).
Keysight U2722A Labview Virtual Instruments (VIs) for characterizing single (IV-curve) or dual transistor configurations using one or 2 SMUs.
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