Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun...

• Updated Jul 17, 2022
• Verilog

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

• Updated Sep 20, 2023
• Python

16-bit Adder Multiplier hardware on Digilent Basys 3

• Updated Aug 3, 2023
• Verilog

An unsupervised transfer learning approach for rare disease transcriptomics

• Updated Jan 27, 2020
• HTML

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

• Updated Jun 6, 2024
• Verilog

The Verilog source code for DRUM approximate multiplier.

• Updated May 4, 2023
• Verilog

Posit Arithmetic Cores generated with FloPoCo

• Updated Jun 25, 2024
• VHDL

🔁 Form multiplier & replicator for Nette Framework

• Updated Feb 11, 2026
• PHP

Booth encoded Wallace tree multiplier

• Updated May 24, 2018
• Verilog

32-bit Wallace and Dadda Tree Multiplier

• Updated Jun 26, 2020
• Verilog

A VHDL code generator for wallace tree multiplier

• Updated Apr 15, 2020
• VHDL

An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

• Updated Jul 27, 2020
• Verilog

This repository contains approximate 8-bit multiplier Verilog code.

• Updated Jun 17, 2020
• Verilog

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

• Updated Jun 1, 2021
• Verilog

Free WordPress Plugin: LCM calculator to find the LCM of two or more numbers. Shows solutions by prime factorization, common multiples, cake/ladder, GCF, division, and Venn diagram. www.calculator.io/lcm-calculator/

• Updated May 15, 2024
• JavaScript

Parameterized and 4-bit carry save multiplier design

• Updated May 22, 2021
• Verilog

Source code for pure combinational 16 bit integer multiplier hardware

• Updated May 22, 2021
• Verilog

Booth's algorithm is a procedure for the multiplication of two signed binary numbers in two's complement notation. This code is a structural\behavioral implementation of the N bit Booth's multiplier in VHDL.

• Updated May 19, 2021
• VHDL

Generator for unsigned n-bit modified Booth encoding Dadda tree multiplier code in VHDL written in C++. Based on https://github.com/HSOgawa/fast-multipliers/.

• Updated Dec 24, 2019
• C++

VHDL implementation of the Booth's multiplication algorithm

• Updated Aug 31, 2019
• VHDL