Custom Altera FPGA designs by Olaoluwa Raji. This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA using VHDL.
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
A go-to repository for exploring, learning, and mastering RTL design and verification.
Implement a synthesizable 32-bit RISC-V RV32I processor with a 5-stage pipeline, hazard detection, and data forwarding for FPGA verification.
Parameterized NxN systolic-array NPU for signed matrix multiplication, implemented in SystemVerilog RTL and verified using UVM, SVA, directed testing, formal verification, functional coverage, and multi-configuration regression.
A modular and fully synthesizable 3-level (L1/L2/L3) cache memory subsystem implemented in SystemVerilog, featuring split L1 caches, a centralized L2, and a Last-Level L3 cache with coherence support.
AtlasRV32 — 32-bit RISC-V pipelined processor with hazard detection and data forwarding, synthesized on Artix-7 FPGA
Formal Verification of Whittaker-Type Zero-Invariant Fields and Receiver Symmetry Breaking in Lean 4 and SystemVerilog.
RISC-V RV32IM Core
RV32I 5-Stage Pipelined CPU
Fully-streaming FPGA Top-of-Book engine with O(log2N) pipelined arbiter achieving 223.4 MHz on Artix-7.
UVM-based verification of an I2C master controller with RTL design, waveform analysis, and Vivado synthesis
RTL Design and Verification of a Parameterized Synchronous FIFO in Verilog with directed, corner, and randomized test cases.
Digital Alarm Clock in Verilog HDL | FSM | ModelSim | Intel Quartus Prime | FPGA RTL Design
Parameterized 16-bit ALU designed in Verilog HDL with functional verification, synthesis, RTL schematic, and gate-level netlist.
8-bit ALU RTL design and verification in SystemVerilog — self-checking testbench, SVA assertions, functional coverage
RTL implementation and class-based verification of a Direct-Mapped Cache Controller using SystemVerilog with a self-checking scoreboard, directed and constrained-random testing.
Configurable AXI arbiter (Round Robin / Fixed Priority + Aging) — RTL verified in Vivado, implemented on Xilinx Artix-7, UVM testbench verified on Xcelium 25.03
Parameterized ×ばつ16 Wallace Tree Multiplier designed in Verilog HDL using Carry Save Adders (CSA), Carry Lookahead Adders (CLA), and multi-stage reduction tree architecture.
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