ReducedLUT: Table Decomposition with "Don't Care" Conditions [FPGA'25]
compression fpga neural-network rtl verilog hardware-acceleration lookup-table ip-generation rtl-generation table-size-reduction hardware-ip
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Mar 30, 2025 - C++
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hardware-ip
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A tool to generate optimized hardware files for univariate functions.
hls rtl hardware-acceleration lookup-table lossless-compression ip-generation function-evaluation table-size-reduction table-based-function-implementation function-implementation hardware-ip
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Apr 5, 2024 - C++
𧩠Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
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Apr 30, 2026 - Python
Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256β4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.
asic fpga pipeline signal-processing rad verilog digital-signal-processing apb ip-core hardware-ip vyges vyges-ip ix-2
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Aug 8, 2026 - SystemVerilog
A fully pipelined digital Hilbert transformer IP block for DSP applications including single sideband modulation, amplitude/phase detection, and quadrature signal processing. Optimized for FPGA and ASIC implementations with configurable precision and maximum throughput.
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Oct 8, 2025 - SystemVerilog
A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.
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Oct 8, 2025 - SystemVerilog
ποΈ Central hub for Vyges community discussions, issues, feature requests, and collaboration
support open-source community documentation asic fpga discussions semiconductor metadata-standards chip-design hardware-development hardware-ip silicon-design ip-repository
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Jul 8, 2025
π Vyges Metadata Specification - Standardized format for hardware IP discovery and integration
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Aug 1, 2026 - HTML
OpenTitan UART IP - Full duplex serial communication peripheral with programmable baud rate, RX/TX buffers, and interrupt support
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Sep 7, 2026 - SystemVerilog
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