Conformance testbench for the Vyges Loom sign-off engines via vyges mcp — deterministic + agentic (GitHub Models)

Homebrew tap for the Vyges CLI — 'brew install vyges/tap/vyges'. Auto-published from the vyges-cli release pipeline.

Ring-oscillator PLL IP for IHP SG13CMOS5L (SG13G2) — Chipalooza Challenge

Capless digitally-trimmable LDO for IHP SG13CMOS5L — Chipalooza Challenge #2 IP.

Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.

A hardware implementation of Meta's MLow audio codec, delivering 2x better quality than Opus at 6kbps while maintaining 10% lower computational complexity. Optimized for RTC applications on resource-constrained devices.

SPI master controller with APB interface, multi-mode support (all SPI modes), configurable FIFO, and interrupt features for ASIC/FPGA integration.

A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz

📋 Vyges Metadata Specification - Standardized format for hardware IP discovery and integration