ReducedLUT: Table Decomposition with "Don't Care" Conditions [FPGA'25]
compression fpga neural-network rtl verilog hardware-acceleration lookup-table ip-generation rtl-generation table-size-reduction hardware-ip
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Mar 30, 2025 - C++
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rtl-generation
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Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required
c-plus-plus arduino simulator fpga vhdl rtl gtkwave risc-v vcd de10-lite vidor rtl-files rtl-generation
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May 29, 2021 - C
Agentic RTL generation pipeline: text/PDF/audio/video → Spec IR → Two-Oracle agent → verified SystemVerilog (GLSVLSI 2026)
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Jun 19, 2026 - Jupyter Notebook
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