Assign binary in VHDL

Question

I'm getting a syntax error near data0_sim in the following code - New to vhdl and confused as I think this should work:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
signal data0_sim : std_logic_vector(8-1 downto 0);
data0_sim <= "00001111";

• user8352: I'd suspect revealing just a bit more might be helpful. Constructing a simple testcase with an architecture declarative item for data0_sim and a concurrent signal assignment statement as shown yields no obvious errors, meaning more context appears needed. The actual error message might help, noting there can be errors that don't point to the character or line position where the actual syntax problem is found.

Answer 1

We can only guess since you haven't told us the syntax error, but from the code posted it MIGHT be:

signal data0_sim : std_logic_vector(8-1 downto 0);
data0_sim <= "00001111";

Now there are two things you might be trying to do here:

1) declare a signal and give it an initial value. The correct syntax for that is:

signal data0_sim : std_logic_vector(8-1 downto 0) := "00001111";

Note that the initialiser uses the variable assignment syntax,to indicate that signal assignment semantics (postponed assignment, event generation) don't apply.

2) declare a signal and later, assign it a value.

The correct syntax for that requires more context : declarations and statements occupy two different spaces in a VHDL unit. This follows programming languages such as Ada, but it is rather different from C.

In VHDL, the context may be an entity/architecture such as:

entity demo is
end demo;
architecture test of demo is
 -- declaration region : your signals, constants, types etc here
 signal data0_sim : std_logic_vector(8-1 downto 0);
begin
 -- statement region : your code here
 data0_sim <= "00001111";
end test;

• user8352: Note you can't always tell an object declaration from an interface declaration - "If no mode is explicitly given in an interface declaration other than an interface file declaration, mode in is assumed." The syntax error could be as simple as trying to assign something to a port formal with a missing mode out. Further, a last formal declaration in the port clause with a missing closing parenthesis on say a std_logic_vector range with a following entity declarative item (e.g. data0_sim) could cause interesting complaints. There's as yet not enough context to address a syntax error.
• user16324: Good points : my answer only covers some causes most likely to trip a beginner, not an exhaustive list.

Answer 2

Why don't you define a component, i.e.

entity example_ent is
 port (data0_sim : out std_logic_vector(7 downto 0));
end example_ent
architecture example_arch of example_ent is
begin
 data0_sim <= "00001111";
end example_arch